Digital Devices

Digital Devices

 Implementing logic circuits  Shorthand notation  Electrical characteristics

Implementing Logic Circuits

 There are several varieties of transistors – the building blocks of logic gates – the most important are:  BJT (bipolar junction transistors) – one of the first to be invented.

 Now largely supplanted by FET (field effect transistors), in particular Metal-oxide semiconductor types (MOSFET’s).  MOSFET’s are of two types: NMOS and PMOS

TTL and CMOS

  Connecting BJT’s together gives rise to a family of logic gates known as TTL Connecting NMOS and PMOS transistors together gives rise to the CMOS family of logic gates.

BJT transistor types MOSFET (NMOS, PMOS) TTL logic gate families CMOS

Electrical characteristics

 TTL   faster strong drive capability  CMOS     lower power consumption simpler to make greater packing density better noise immunity •

Complex ic’s contain many millions of transistors.

•

If constructed entirely from TTL type gates would melt

•

A combination of technologies may be used.

•

CMOS has become most popular and has had greatest development

Electrical characteristics of logic families



Important characteristics are:

 

V OHmin V IHmin min value of output recognised as a ‘1’ min value input recognised as a ‘1’

 

V ILmax max value of input recognised as a ‘0’ V OLmax max value of output recognised as a ‘0’

logic 1 indeterminate input voltage 

Values outside the given range are not allowed.

logic 0

Noise Margin

   If noise in the circuit is high enough it can push a logic 0 up or drop a logic 1 down into the “illegal” region This is the magnitude of the voltage required to reach this level is the noise margin Noise margin for logic high is: N MH = V OHmin – V IHmin logic 1 indeterminate input voltage logic 0 Vohmin Vihmin Vilmax Volmax

Further Important Characteristics

 The

propagation delay

(t pd ) which is the time taken for a change at the input to appear at the output  The

fanout

, which is the maximum number of inputs that can be driven successfully to either logic level before the output becomes invalid

TTL - Example SN74LS00

 

Recommended operating conditions

 V cc supply voltage 5V ± 0.5 V  input voltages V IH V IL = 2V = 0.8V

Electrical Characteristics

   output voltage (worst) Maximum input currents I V OH V OL = 2.7V

= 0.5V IL I IH = -0.4mA

= 20µA propagation delay t pd = 15 nS  noise margins  Fan-out Input Range for 1 for a logic 0 = 0.3V

for a logic 1 = 0.7V

20 TTL loads Input Range for 0 5 Volt 2.7

2.0

0.8

0.5

0 Volt Output Range for 1 Output Range for 0

Electronic Combinational Logic

Within each of these families there is a large variety of different devices  We can break these into groups based on the number gates per device Acronym SSI MSI LSI VLSI ULSI Description Small-scale integration Medium-scale Large-scale Very large-scale Ultra large scale No Gates <12 12 – 100 100 – 1000 1000 – 1m > 1m Example 4 NAND gates Adder 6800 68000 486/586 For this course we will just look at the first 2: SSI and MSI

SSI Devices

 Each package contains a code identifying the package

N74LS00

Manufacturers Code N = National Semiconductors SN = Signetics Specification Family L LS H Member 00 = Quad 2 input NAND 02 = Quad 2 input Nor 04 = Hex Invertors 20 = Dual 4 Input NAND

Connections on 74LS00

 Show how a single 74LS00 could be used to implement the function P = A.B+A.C

14 13 12 11 10 9 8 1 2 3 4 5 6 7

Connections on 74LS00

 Can be done in three steps:  Draw the equivalent circuit  Convert to NAND gates only  Work out the pin connections

Pin Connections

 One solution, check it!

   Inputs  

A connects to 1,2 and 13 B connects to 12



C connects to 5

Outputs 

P connects to 8.

Pins 

11 to 10

 

3 to 4 6 to 9

14 13 12 11 10 9 8 1 2 3 4 5 6 7

MSI Devices

 Commonly used functions such as the adder and the BCD-to-seven-segment display are implemented as MSI devices

BCD to SSD

BCD inputs

Programmable Logic Devices

  Programmable devices have their functionality programmed before they are first used.

Range in complexity from 100’s to 10,000’s of logic gates.

PLD’s

 Commonly use logic gates based on diodes: Vdd – logic 1 eg AND gate Ry a both at logic 1 b y = a.b

if either a or b is pulled down to Vss, logic 0, then y is pulled to zero also More inputs can be made by adding more diodes.

Source: Bebop to the Boolean Boogie, Clive Maxfield, Technology Publishing, ISBN 1-878707-22-1

Exercise

 Consider how an OR gate might be implemented: a b Ry a and b are at logic ?

output y is on upper or lower line Vdd – logic 0

Fusible link PLD’s

  Each diode has an associated link (fuse) The can be “blown” with a high voltage pulse  Thus the arrays of diodes can be programmed (one-time).

PLD’s

Most of these devices are based on a two level structure (sum of products form).

Inputs

AND plane

products

OR plane

outputs

In practice this might be represented as:

inputs

A B C D

PLD notation

 The fusible links are made at the x’s, otherwise blown.

A.C + B.C

D + A outputs

Inverted inputs

A B

inputs A.B + A.B

= B outputs A + B

PLD’s



The main types of PLD include:

 PLA’s (programmable logic arrays)  PAL’s (programmable array logic)  PROM’s (programmable read only memory)

PLA’s

A programmable logic array (PLA) has all links programmable in both AND and OR arrays.

Very flexible.

Many applications don’t require such flexibility A B

PALs

 AND plane programmable  OR plane fixed  Not so flexible  Operate faster because hard wired OR’s switch quicker than programmed links.

B A AABB F4 F1 1 2 3 F5 F8 programmable links P

PAL’s

    P = A.notB + notA.B

Use gate 1 to implement the 1st product term and gate 2 to implement the second First term blow F2 and F3 Second term blow F5 and F8 B A AABB F4 F1 F5 F8 1 2 3 P

PALs Shorthand Notation

A B C D E P P = A.C.D

PROMs

 AND array is pre-defined  OR array is programmable  Output of AND plane contains a signal for each of the possible input combinations  Memory device where each address applied to inputs returns a programmed value address ROM data

PROM

address 0 address 1 address 2 address3 A B programmable OR array

PROMs

Example: The full adder 0 1 1 1 1 Cin A B S Cout 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 0 1 1 1 Cin A B decoder 111 110 101 100 011 010 001 000 sum Cout

Reprogrammable PLD’s

 EPROMS are like PROM’s except that they can be re used.

 Ultra-violet light is used to restore the fusible links   This is shone through a quartz window on top of the chip Useful for testing and debugging before PROM’s are manufactured.

Custom and Semi-custom Integrated Circuits

 Custom Chips: where the chips are designed from scratch  Very time consuming and expensive (Need to manufacture >10 5 to be economic)  Semi-custom Chips: where most of the design is already done and designer only has to make the final connections

What you should be able to do:

    State the principal characteristics of TTL and CMOS logic gate families.

Define key terms such as:   fan-out propagation delay  noise margin Describe the key features of the range of PLD’s: PLA, PAL, PROM.

Convert a (simple) shorthand PAL diagram to a logic expression.