Transcript Digital Circuit Design - Prince of Songkla University

Digital Circuit Design on FPGA
Nattha Jindapetch
November 2008
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Agenda
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Design trends
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IC technology revolution
Design styles
System integration
Programmable logic
FPGA design flow & Tools
LABs
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IC Technology Revolution
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Invention of the Transistor
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1947: first point contact transistor at
Bell Labs
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The First Integrated Circuit
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1966: ECL 3-Input gate at Motorola
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MOS Integrated Circuits
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1970’s processes usually had only nMOS
transistors
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Inexpensive, but consume power while idle
Intel 1101
Intel 4004 4-bit Proc
256-bit SRAM
1000 Trs, 1 MHz operation
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High Performance Processors
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2001: Intel Pentium Microprocessor
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42 M transistors,
1.5 GHz operation
CMOS, Low power
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Moore’s Law
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Transistor counts have doubled every 2 years
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
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Corollaries
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Many other factors grow exponentially
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Ex: clock frequency, processor performance
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Evolution of a Revolution
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www.intel.com
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Design Styles
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Design Styles
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Full-custom ASIC
Cell-based ASIC
Gate array
Programmable logic
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Field programmable gate array (FPGA)
Programmable logic device (PLD)
Complex PLD (CPLD)
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Full-Custom ASIC
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layout-based
the designer draws
each polygon “by
hand”
More compact design
but longer design
time
only for analogue and
high(est) volumes
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Cell-Based ASIC
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used predefined
building blocks (“cells”)
designer creates a
schematic that
interconnects these
cells
layout = placement &
interconnection of cells
for “functionality” or
“time-to market” driven
design
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Gate Array
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Each chip is
prefabricated with
an array of identical
gates or cells.
The chip is
“customized” by
fabricating routing
layers on top.
Time to market, cost
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Field programmable gate array
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Chips are prefabricated
with logic blocks and
interconnects.
Logic and interconnects
can be programmed
(erased and
reprogrammed) by users.
No fabrication is needed.
Cost efficient for
medium complexity (< 1M
gates) designs
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PLD and CPLD
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Programmable Logic Device
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(PLD, PLA, PAL, ...)
AND-OR combinatorial logic, plus FF
designer writes Boolean equations
Small complexity only
Complex PLD (CPLD)
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several PLD blocks
programmable interconnection matrix
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Trends in Design styles
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More complex system
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Digital and Analog IC (Mixed Signal)
Hardware and Software Co-design
SoC, SoPC
Resulting in …
 Higher abstract design level
 Advanced design tools to automate complex
designs
 Short design time to compete market share
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Why HW/SW Co-design?
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Hardware (ASIC, FPGA)
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Software (Processor)
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Fast
But very expensive
Flexible
But slow
Hardware + Software = Good solution?
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Requirements?
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Example of Digital Camera
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System Integration
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System Integration
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Benefits
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Less components
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Less inter-chip interconnects
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Reliability
Power consumption
Board design, fabrication and assembly costs
Smaller system volume (in cm2) and weight
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Component costs
Board size and cost
Assembly and testing costs
Higher integration rate
Smaller case costs
Smaller transport costs
In high volumes (in pcs), also lower circuit costs
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SoP
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System-on-Package (SoP) or System-inPackage (SiP) are advanced multi-chip
packaging technology complementing SoC.
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SoC
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System-on-Chip –one term, many definitions
“IBM definition”: a single-chip system containing
analog, digital and MEMS (micro-electromechanical system) parts
 “Lucent definition”: a single-chip system containing
analog and digital parts
 “Synopsys definition”: a single-chip digital system
SoC, System-on-Chip is a relatively complex
standalone system on a single semiconductor chip
containing at least one processor, maybe some analog
or even electro-mechanical parts, where the design
needs to address on-chip communication
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SoPC
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System-on-a-Programmable Chip (SOPC) term
coined by Synopsys
SoPC is a FPGA technology based user
programmable solution
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P&R and programming done by the user
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No delay on prototype production
No delay on mass production start
No NRE (production start) costs
Production tests done by the IC vendor
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Design resource and time savings in the design flow
Quick and cheap modifications
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SoC vs SoPC
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SoC manufacturing is costly
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Foundries more and more expensive
Mask costs for fine-grain lithography are increasing
Silicon vendors concentrate on big customers with big
quantities
Very few multi-project prototype services available
Malfunction will cost a lot of money and time
Full-wafer prototype round may cost even 500,000 ... 1M €
FPGA-type solutions are also evolving
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On-chip processor cores
Multi-million gate capacity
Some vendors also provide coarse-grain reconfigurability
FPGA-based SoC-type platforms thus have a growing niche
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Programmable Logic
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Programmable Logic
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Programmable digital integrated circuit
Standard off-the-shelf parts
Desired functionality is implemented by configuring onchip logic blocks and interconnections
Advantages (compared to an ASIC):
 Low development costs
 Short development cycle
 Device can (usually) be reprogrammed
Types of programmable logic:
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Complex PLDs (CPLD)
Field programmable Gate Arrays (FPGA)
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CPLD
Architecture and Examples
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PLD - Sum of Products
Programmable AND array followed by fixed fan-in OR gates
A
B
C
Programmable switch or fuse
f1  A  B  C  A  B  C
f2  A  B  A  B  C
AND plane
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PLD - Macrocell
Can implement combinational or sequential logic
Select
A
B
Enable
C
f1
Flip-flop
MUX
D
Q
Clock
AND plane
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CPLD Structure
Integration of several PLD blocks with a
programmable interconnect on a single chip
PLD
Block
•
•
•
•
•
•
I/O Block
PLD
Block
I/O Block
I/O Block
•
•
•
Interconnection Matrix
I/O Block
•
•
•
PLD
Block
PLD
Block
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CPLD Example – Altera MAX7000
EPM7000 Series Block Diagram
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CPLD Example –Altera MAX7000
EPM7000 Series Device Macrocell
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FPGA Architecture
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FPGA - Generic Structure
Logic
block
FPGA building blocks:
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I/O
I/O
I/O
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Programmable logic blocks
Implement combinatorial and
sequential logic
Programmable interconnect
Wires to connect inputs and
outputs to logic blocks
Programmable I/O blocks
Special logic blocks at the
periphery of device for
external connections
Interconnection switches
I/O
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Other FPGA Building Blocks
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Clock distribution
Embedded memory blocks
Special purpose blocks:
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DSP blocks:
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Hardware multipliers, adders and registers
Embedded
microprocessors/microcontrollers
High-speed serial transceivers
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FPGA – Basic Logic Element
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LUT to implement combinatorial logic
Register for sequential circuits
Additional logic (not shown):
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Carry logic for arithmetic functions
Expansion logic for functions requiring more than 4
Select
inputs
Out
A
B
C
D
LUT
D
Clock
Q
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Look-Up Tables (LUT)
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Look-up table with N-inputs can be used to implement
any combinatorial function of N inputs
LUT is programmed with the truth-table
A
B
C
D
Z
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
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0
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Truth-table
A
B
C
D
LUT
Z
LUT implementation
A
B
Z
C
D
Gate implementation
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LUT Implementation
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X1
X2
Example: 3-input
LUT
Configuration memory
cells
Based on
multiplexers (pass
transistors)
LUT entries stored
in configuration
memory cells
X3
0/1
0/1
0/1
0/1
0/1
F
0/1
0/1
0/1
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Programmable Interconnect
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Interconnect hierarchy (not shown)
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Fast local interconnect
Horizontal and vertical lines of various lengths
LE
LE
Switch
Matrix
LE
LE
Switch
Matrix
LE
LE
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Switch Matrix Operation
Before Programming
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6 pass transistors per
switch matrix interconnect
point
Pass transistors act as
programmable switches
Pass transistor gates are
driven by configuration
memory cells
After Programming
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Special Features
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Clock management
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PLL,DLL
Eliminate clock skew between external clock input
and on-chip clock
Low-skew global clock distribution network
Support for various interface standards
High-speed serial I/Os
Embedded processor cores
DSP blocks
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Configuration Storage Elements
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Static Random Access Memory (SRAM)
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Flash Erasable Programmable ROM (Flash)
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each switch is a pass transistor controlled by the state of an
SRAM bit
FPGA needs to be configured at power-on
each switch is a floating-gate transistor that can be turned off
by injecting charge onto its gate. FPGA itself holds the program
reprogrammable, even in-circuit
Fusible Links (“Antifuse”)
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Forms a forms a low resistance path when electrically
programmed
one-time programmable in special programming machine
radiation tolerant
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FPGA Vendors & Device Families
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Xilinx
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Virtex-II/Virtex-4: Featurepacked high-performance
SRAM-based FPGA
Spartan 3: low-cost feature
reduced version
CoolRunner: CPLDs
Altera
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Stratix/Stratix-II
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Low-cost feature reduced
version for cost-critical
applications
MAX3000/7000 CPLDs
MAX-II: Flash-based FPGA
Actel
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Anti-fuse based
FPGAs
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Radiation tolerant
Flash-based FPGAs
Lattice
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High-performance SRAM-based
FPGAs
Cyclone/Cyclone-II
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Flash-based FPGAs
CPLDs (EEPROM)
QuickLogic
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ViaLink-based
FPGAs
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State of the Art in FPGAs
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Xilinx’s top of the line FPGA
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65nm process technology
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Serial connectivity
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550MHz RAM blocks
6-input LUTs
Ethernet MACs
Rocket I/O serial 6.5 GBps
PCI Express endpoint
Enhanced DSP blocks (25x18-bit MAC)
1760 pin BGA with 1200 I/O
EasyPath
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FPGA Design Flow
Xilinx Design Flow
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LABs
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Lab1: Introduction
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Quick start
Synthesis results
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RTL schematic
Technology schematic
Device utilization summary
Timing summary
Simulation
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Behavioral
Post-Place and Route (PAR) Simulation
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References
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Theerayod Wiangtong, “Design Trends on Digital
System Design”, Lecture note, Electronic
Department, Mahanakorn University of Technology,
2004
Fank Mayer, “High-Level IC Design”, Fraunhofer
IIS, Erlangen, Germany, 2004
Stefan Haas, “FPGAs”, CERN Technical Training
2005
Xilinx University Program,
http://www.xilinx.com/support/educationhome.htm
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