Transcript Document

Introduction to ComputerAided Hardware Design
Life is like a symphony. It all depends on how you conduct it
CMSC411/Computer Architecture
These slides and all associated material are
© 2003 by J. Six and are available only for
students enrolled in CMSC411.
Life is like a symphony. It all depends on how you conduct it.
CMSC411 – Computer Architecture / © 2003 J. Six
Use and Distribution Notice
Possession of any of these files implies understanding and
agreement to this policy.
The slides are provided for the use of students enrolled in Jeff
Six's Computer Architecture class (CMSC 411) at the University of
Maryland Baltimore County. They are the creation of Mr. Six and
he reserves all rights as to the slides. These slides are not to be
modified or redistributed in any way. All of these slides may only
be used by students for the purpose of reviewing the material
covered in lecture. Any other use, including but not limited to, the
modification of any slides or the sale of any slides or material, in
whole or in part, is expressly prohibited.
Most of the material in these slides, including the examples, is
derived from slides developed by Prof. Gao at the University of
Delaware. Credit is hereby given to the author of these slides for
much of the content. This content is used here for the purpose of
presenting this material in CMSC 411, designed in a similar model.
CMSC411 – Computer Architecture / © 2003 J. Six
Historical Perspective on
Hardware Design
The market for digital hardware is an extreme
market. It demands high performance, lower
power consumption, and smaller footprint.
Technology is evolving at a fantastic rate.
This includes an ever decreasing feature size,
tighter VLSI integration, new mounting and
new packaging technologies.
This demands a new design methodology…
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must deal with greater complexity
decreasing time-to-market schedules
CMSC411 – Computer Architecture / © 2003 J. Six
The New Design Methodology
We require…
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increased efficiency
tools to capture, understand, and maintain a
design
designs that are not open to interpretation
an open and widely used standard
portability and reusability
hierarchical design capabilities
modular design capabilities
easy of use for design, modeling, simulation
CMSC411 – Computer Architecture / © 2003 J. Six
Enter VHDL
VHDL is a language for describing models of
hardware systems (one of many – but the
most popular).
Using VHDL and programmable hardware, we
can use a fix step design process…
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Define the requirements.
Describe the designs in VHDL.
Simulate the VHDL source code.
Synthesize, optimize and place-and-route the
design for our target programmable device.
Simulate the post-layout design.
Program the target programmable device.
CMSC411 – Computer Architecture / © 2003 J. Six
Design Requirements
To form a useable set of design requirements,
we need to clearly identify and define the
objectives and requirements.
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functionality?
timing requirements?
set-up and hold times?
clock-to-output times?
minimal operating frequency?
critical path delays?
and so on…
Modern Hardware
Design Process
CMSC411 – Computer Architecture / © 2003 J. Six
Simulation is a source code simulation using a
VHDL simulator.
Synthesis flattens the hierarchical design and
transforms it into a monolithic RTL representation.
Optimization then makes that monolithic design
as efficient as it can.
Once that is done, the optimized design is
subjected to a layout tool…
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Fitting – this involves the translation from the RTL to a
minimum sum of product expression for programming
into a CPLD programmable device.
Place-and-route – this involves the translation from
RTL to a FPGA device’s specific requirements.
CMSC411 – Computer Architecture / © 2003 J. Six
Example Synthesis Process
CMSC411 – Computer Architecture / © 2003 J. Six
Post-Layout Simulation
After the appropriate layout process has
completed, timing information is now present
in the design.
The synthesis and layout tools figure out
timing characteristics based on the device
being programmed.
This post-layout code can then be simulated
to see if the finished device meets all of the
design objectives.
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If it does, excellent!
If not, a different target device could be used, or
the VHDL code could be modified.
CMSC411 – Computer Architecture / © 2003 J. Six
Device
selection
VHDL
design
Synthesis
directives
Synthesis software
Example Design
Tool Flow
Netlist
or
equations
Fitter or place & route routines
Postlayout
simulation
model
(VHDL or
other
format)
Test
bench
or other
stimulus
Report
file:
resource
summary;
static
timing
analysis
Simulation software (VHDL or other simulator)
Waveform
Data file
Device
programming
file:
(for example,
JEDEC
format)
CMSC411 – Computer Architecture / © 2003 J. Six
Programmable Devices
Source: Dataquest
Logic
Standard
Logic
Programmable
Logic Devices
(PLDs)
SPLDs
(PALs)
ASIC
Gate
Arrays
CPLDs
Cell-Based
ICs
Full Custom
ICs
FPGAs
SPLD – simple programmable logic device
CPLD – complex programmable logic device
FPGA – field programmable gate array
CMSC411 – Computer Architecture / © 2003 J. Six
FPGAs
A FPGA is a field programmable gate array.
This is an array of logic cells that are connected via
routing channels.
Each logic cell is programmable, as are the routing
channels.
Each logic cell is a lookup table (LUT) with some
registers.
Most FPGAs have special I/O cells and
interconnections to onboard RAM.
Once the design has been subjected to place-androute, the netlist is then given to a programming
device which programs the FPGA. The FPGA then
functions as our hardware until it is reprogrammed.
CMSC411 – Computer Architecture / © 2003 J. Six
FPGA Advantages
FPGAs have a number of advantages
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Good performance (they are fast).
High density and high capacity (they can
act as large pieces of hardware).
They are easy to use.
They are programmable and
reprogrammable (a huge amount of times).
They are not very expensive.
CMSC411 – Computer Architecture / © 2003 J. Six
CPLDs versus FPGAs
A CPLD is a complex programmable logic device
(like a PLA or PAL, but somewhat more complex).
Complex Programmable Logic Device
Field-Programmable Gate Array
Architecture
PAL/22V10-like
More Combinational
Gate array-like
More Registers + RAM
Density
Low-to-medium
0.5-10K logic gates
Medium-to-high
1K to 500K system gates
Performance
Predictable timing
Up to 200 MHz today
Application dependent
Up to 135MHz today
Interconnect
“Crossbar”
Incremental
CMSC411 – Computer Architecture / © 2003 J. Six
A Sample CPLD
Looking into a sample CPLD (XC9500)…
3
JTAG
Controller
JTAG Port
In-System
Programming Controller
Function
Block 1
I/O
I/O
I/O
I/O
Blocks
I/O
Global
Clocks
Global
Set/Reset
Global
Tri-States
Function
Block 2
FastCONNECT
Switch Matrix
Function
Block 3
3
1
Function
Block 4
2 or 4
CMSC411 – Computer Architecture / © 2003 J. Six
A Sample FPGA
Looking into a sample FPGA (the Xilinx XC4000)…
CLB
Slew
Rate
Control
CLB
Switch
Matrix
D
CLB
Input
Buffer
Programmable
Interconnect
C1 C2 C3 C4
H1 DIN S/R EC
S/R
Control
DIN
G
Func.
Gen.
SD
F'
H'
EC
RD
1
F4
F3
F2
F1
H
Func.
Gen.
F
Func.
Gen.
Y
G'
H'
S/R
Control
DIN
SD
F'
D
G'
Q
H'
1
H'
K
Q
D
G'
F'
Vcc
Output
Buffer
CLB
Q
G4
G3
G2
G1
Q
Passive
Pull-Up,
Pull-Down
EC
RD
X
Configurable
Logic Blocks (CLBs)
D
Delay
I/O Blocks (IOBs)
Pad
CMSC411 – Computer Architecture / © 2003 J. Six
Complex Logic Blocks
Each XP4000 Complex Logic Block…
C1 C2 C3 C4
2 four-input function
generators (LUTs)
- act as a 16x1 RAM
or as logic function
2 registers
- Each can be
configured as a
flip/flop or a latch
- synchronous and
asynchronous
Set/Reset
H1 DIN S/R EC
S/R
Control
G4
G3
G2
G1
DIN
F'
G'
G
Func.
Gen.
SD
H
Func
.Gen.
F
Func.
Gen.
EC
RD
G'
H'
Y
S/R
Control
DIN
SD
F'
G'
D
Q
XQ
H'
1
H'
K
YQ
H'
1
F4
F3
F2
F1
Q
D
F'
EC
RD
X
CMSC411 – Computer Architecture / © 2003 J. Six
Function Generators / LUTs
Each function generator in the XC4000…
Combinatorial Logic
Look Up Table
4-bit address
A
B
Z
C
D
 Capacity is limited by number of
inputs, not complexity
 Each function generator can act
as 4 input LUT or as high speed
synchronous dual port RAM
WE
G4
G3
G2
G1
G
Func.
Gen.
A B C D
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Z
0
0
0
1
1
1
. . .
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
1
CMSC411 – Computer Architecture / © 2003 J. Six
Input/Output Blocks
The I/O Blocks in the XC4000…
CMSC411 – Computer Architecture / © 2003 J. Six
FPGA Routing
Most FPGAs have a routing network that
connects the complex logic blocks and I/O
blocks (in a programmable manner).
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
CLB
CMSC411 – Computer Architecture / © 2003 J. Six
Design Flow for ASICs
Although we have discussed targeting
programmable logic devices, VHDL can also be
synthesized and subjected to layout for
fabrication as an ASIC.
This requires a different set of tools but follows
the same design process.
Typical flow…
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Design in VHDL and simulate.
Synthesize and layout for FPGAs.
Simulate and then program FPGA.
Test the FPGA hardware.
Synthesize and layout for ASIC.
Simulate.
Send to fabrication.