Microelectronic System Design

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Transcript Microelectronic System Design

3. ASIC and SOC Design Methods: Structured VLSI Design

Spring 2009 Rajesh K. Gupta

 Circuit Styles  The evolving ASIC Design Methodology

Outline

 References:  Basic Logic Families, Kerry Bernstein, Ch. 7, of A. Chandrakasan

et. al.

book  Chapter 11 of Rabaey book

Basic Logic Families

 Circuit Styles  Different possible circuit

topologies

for a given logic function (from the same set of basic transistor devices)  even within CMOS:

compatible

CMOS styles  Choice determined by design criteria: performance, power consumption, testability, ease of design (analysis)  Available styles  Nonclocked logic (clocked logic discussed after clocking)  example: static combinatorial CMOS, differential cascode voltage-switch logic, pass-transistor logic  generally: low power, ease of automated synthesis, easy timing analysis, reliability and noise immunity, defect tolerance, migration across process.

 Reliability because nodes maintain values (never left to float), direct control of nodal values (noise immunity), switch points can be varied.

Nonclocked: Static Combinatorial CMOS

 Operate under “push-pull” action  Transfer function  similar to the inverter transfer function  unity gain point (UGP)  point on the transfer function where slope is -1  a circuit will attenuate inputs less than the lower UGP and amplify inputs higher than the lower UGP  switch point (SWP)  where Vin = Vout  can be skewed by the effective device sizing by hastening transition in a given direction  noise margin  is the difference between the least positive up level of the preceding stage and the upper UGP of the given stage  or the most positive down level of the previous stage and the lower UGP of the given stage.

Static CMOS

 Delay variations  by the input pattern, by switching history  by the active fanout load  depending upon the channel state, gate-substrate capacitance changes (towards inversion gate-substrate capacitance drops)  signal coupling in interconnect changes fanout load  false switching (consumes about 15% of the total power)  Design rules  Alpha ratio:  ratio of the total output capacitance on a given stage divided by its total input capacitance; (2.7 produces minimum PDP)  Beta ratio:  ratio of a given stage’s PFET W/L to its NFET W/L  NAND n-stack design:  body effect on the top device decreases its drive  device tapering and signal positioning.

Domino CMOS

 Domino logic is evaluated through single-sided transitions  no need for complimentary logic implementations  generally N-FET evaluation trees (smaller area)  To ensure single transitions, all outputs are inverted so that the inputs only make a transition from low to high  several issues related to capacitive coupling, noise immunity and false discharges

Pass-Gate Logic

 Logic evaluation by signal coupling  rather than by signal evaluation and redriving  Generally lower capacitive loads  However, many liabilities  limited fan-in capability  current discharge to ground through a pass-gate must be limited to achieve acceptable low levels at the receiver  excessive fan-out  the driver to pass gates (for example, output inverter driving subsequent pass gates) must be sized for all the paths its serves  noise vulnerability  interconnect coupling can be propagated through a pass gate  Body bias effects reduce available drive  Path protection need for decoders: when used as mux, gate inputs are needed to ensure paths are maintained.

Improved by complementary pass-gate logic (CPL)

Structured VLSI Design

Four Phases in Creating a Chip

The Design Problem

Source: sematech97

A growing gap between design complexity and design productivity

VLSI-design Tools & Methodologies

 Goal is to reduce complexity, increase productivity, and increase chances of a working chip  Key is the use of

Constraints

and

Abstractions

 Constraints  help automate the procedure by simplifying the problem  Abstractions  collapse detail and arrive at a simpler problem to deal with  Different design methodologies  different types of constraints and trade-offs  choice driven by economics!

Design Domains

 Behavioral  what a system does  Structural  how entities are connected together to perform the behavior  Physical (geometrical)  how to build a structure that has the required connectivity to implement the prescribed behavior

Levels of Design Abstractions for Each Design Domain

 Architectural  Algorithmic  Module or functional block  Logical  Switch  Circuit  Device  etc.

Design Abstraction Levels

SYSTEM

MODULE GATE

V in V out S n+ G

DEVICE

Design Methodology

  Design process traverses iteratively between behavior, structure, and geometry abstractions CAD tools providing more and more automation

A Simplified Flow

Implementation Choices

Digital Circuit Implementation Approaches Custom Cell-based Semicustom Array-based Standard Cells Compiled Cells Macro Cells Pre-diffused (Gate Arrays) Pre-wired (FPGA's)

Transition to Automation and Regular Structures Intel 4004 (‘71) Intel 8080 Intel 8085 Intel 8286 Intel 8486

Cell-based Design (or standard cells)

Routing channel requirements are reduced by presence of more interconnect layers

Standard Cell - Example

3-input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time

Automatic Cell Generation

Initial transistor geometries Placed transistors Routed cell Compacted cell

Adapted from Digital Integrated Circuits (2 nd

Courtesy Acadabra

Finished cell

MacroModules

256  32 (or 8192 bit) SRAM Generated by hard-macro module generator

“Soft” MacroModules

“Intellectual Property”

Semicustom Design Flow

Pre-Layout Simulation Design Capture HDL Logic Synthesis Behavioral Structural Post-Layout Simulation Circuit Extraction Floorplanning Placement Routing Tape-out

Physical

The “Design Closure” Problem

Iterative Removal of Timing Violations (white lines)

Courtesy Synopsys

Macromodules Fixed netlists

Integrating Synthesis with Physical Design

RTL (Timing) Constraints Physical Synthesis Netlist with Place-and-Route Info Place-and-Route Optimization Artwork

Late-Binding Implementation

Digital Circuit Implementation Approaches Custom Cell-based Standard Cells Compiled Cells Semicustom Macro Cells Array-based Pre-diffused (Gate Arrays) Pre-wired (FPGA's)

Array-based Pre-diffused (Gate Arrays) Pre-wired (FPGA's)

Gate Array — Sea-of-gates

V D D

rows of uncommitted cells

GND

polysilicon metal Uncommited Cell routing channel

Out

Committed Cell (4-input NOR)

PMOS Oxide-isolation

Sea-of-gate Primitive Cells

PMOS NMOS NMOS NMOS Using oxide-isolation Using gate-isolation

Prewired Arrays

Classification of prewired arrays (or field-programmable devices):

 Based on Programming Technique  Fuse-based (program-once)  Non-volatile EPROM based  RAM based  Programmable Logic Style  Array-Based  Look-up Table  Programmable Interconnect Style  Channel-routing  Mesh networks

 Normally high resistance (> 100 M  )  on application of appropriate voltage, the antifuse is changed permanently to a low resistance structure (200 500  )

Antifuse

Array-Based Programmable Logic

Programmable OR array

Fixed OR array Programmable AND array

PLA

Fixed AND array

0 PROM Indicates programmable connection Indicates fixed connection

Programmable AND array

PAL

Programming a PROM

: programmed node

NA NA f

A B

0 1

S F

2-input mux as programmable logic block

Configuration

0 0 0 0

X Y Y

1 1 1

X Y Y

0 0 1 0 0 1

0 1 1

X Y X X X Y

X Y XY XY XY X

X Y Y

Logic Cell of Actel Fuse-Based FPGA

A B SA C D SB S

1 1 1 1

Look-up Table Based Logic Cell

Out In 00 01 10 11 Out 00 1 1 0 ln1 ln2

LUT-Based Logic Cell

4 C 1 ....C

4 D 4 D 3 D 2 D 1 Logic function of xxx F 4 F 3 F 2 F 1 x xxxxx Logic function of xxx

Xilinx 4000 Series

xx Logic function of xxx x xx xx xx xx xxxx xxxx xxxx Bits control x xx x xxxx xx x x xx xx xx xx xx xx x Bits control x xx x x xxxx xx H P xx xx x Multiplexer Controlled by Configuration Program x

Adapted from Digital Integrated Circuits (2 nd

Courtesy Xilinx

Array-Based Programmable Wiring

Interconnect Point Programmed interconnection

Cell

Input/output pin Horizontal tracks Vertical tracks

Mesh-based Interconnect Network

Switch Box Connect Box Interconnect Point Courtesy Dehon and Wawrzyniek

Transistor Implementation of Mesh

Courtesy Dehon and Wawrzyniek

Hierarchical Mesh Network

Use overlayed mesh to support longer connections Reduced fanout and reduced resistance

Courtesy Dehon and Wawrzyniek

Primary inputs

EPLD Block Diagram

Macrocell

Adapted from Digital Integrated Circuits (2 nd

Courtesy Altera

Altera MAX

Adapted from Digital Integrated Circuits (2 nd

From Smith97

LAB1

Altera MAX Interconnect Architecture

column channel row channel t PIA LAB2 LAB PIA t PIA LAB6

Array-based (MAX 3000-7000) Mesh-based (MAX 9000)

Adapted from Digital Integrated Circuits (2 nd

Courtesy Altera

Field-Programmable Gate Arrays Fuse-based

I/O Buffers Program/Test/Diagnostics Vertical routes Standard-cell like floorplan Rows of logic modules Routing channels I/O Buffers

Xilinx 4000 Interconnect Architecture

CLB 2 12 Quad 4 4 8 4 8 4 2 Long Global Clock Long Double Single Global Clock Carry Chain Direct Connect 3 12 8 4 3 Quad Single Double Long Direct Connect Long

Adapted from Digital Integrated Circuits (2 nd

Courtesy Xilinx

RAM-based FPGA

Adapted from Digital Integrated Circuits (2 nd

Courtesy Xilinx

Xilinx XC4000ex

Architecture ReUse

 Silicon System Platform  Flexible architecture for hardware and software  Specific (programmable) components  Network architecture  Software modules   Rules and guidelines for design of HW and SW Has been successful in PC’s  Dominance of a few players who specify and control architecture  Application-domain specific (difference in constraints)  Speed (compute power)  Dissipation  Costs  Real / non-real time data

Platform-Based Design

 A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer  New platforms will be defined at the architecture micro-architecture boundary  They will be component-based, and will provide a range of choices from structured-custom to fully programmable implementations  Key to such approaches is the representation of communication in the platform model

Adapted from Digital Integrated Circuits (2 nd

Source:R.Newton

Heterogeneous Programmable Platforms

FPGA Fabric Embedded memories Embedded PowerPc Hardwired multipliers

Xilinx Vertex-II Pro

High-speed I/O

Adapted from Digital Integrated Circuits (2 nd

Courtesy Xilinx

 Hierarchy