Transcript Department of Electronic Engineering, FJU Chapter 4

Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Chapter 4
Combinational Logic
Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Combinational Logic Circuit
 Combinational circuit: logic circuit whose outputs at
any time are determined directly and only from the
present input combination.
 A combinational circuit performs a specific
information-processing operation fully specified
logically by a set of Boolean functions.
 Sequential circuit: one that employ memory elements
in addition to (combinational) logic gates—their
outputs are determined from the present input
combination as well as the state of the memory cells.
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Introduction
 The state of the memory elements, in turn, is a
function of the previous inputs (and the previous
state).
 Its behavior therefore is specified by a time sequence
of inputs and internal states.
 In many applications, the source and the destination
are storage registers.
 A combinational circuit also can be described by m
Boolean functions, one for each output variable.
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Block Diagram of a Combinational
Circuit
n inputs
Combinational
Circuit
m outputs
Fig. 4-1: Block Diagram of Combinational Circuit
4
ABC
(A + B + C)(AB + AC + BC)’ + ABC
Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Analysis Procedure
A+B+C
AB
AC
(AB + AC + BC)’
AB + AC + BC
BC
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Design Procedure
1. Define the problem.
2. Determine the number of input/output
variables.
3. Assign letter symbols to input/output variables.
4. Derive the truth table and defines the required
relationships between inputs & outputs via KM.
5. Obtain the simplified Boolean function for each
output.
6. Draw the logic diagram.
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Adder
 The most basic arithmetic operation is the addition of 2
bits. A combinational circuit that
performs this operation is called a half-adder.
 A combinational circuit that performs the addition of 3
bits is called a full-adder, which
can be implemented by 2 half-adders.
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Half Adder
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Half Adder-Various Implementation
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Full Adder
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Full Adder
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Implementation of FA
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Implementation of FA
S = z (x  y) = z’(xy’ +xy’) + z (xy’ +x’y)’ = z’(xy’ +x’y) +
z(xy + x’y’) = xy’z’ + x’yz’ + xyz + x’y’z
The carry output is
C = z(x’y + xy’) + xy = xy’z + x’yz + xy
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Binary Subtractor
Subtraction = addition of minuend and 2’scomplemented subtrahend.
Also can implement subtraction directly—with
half-subtractors and full-subtractors.
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Subtractor
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Code Conversion Example
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Maps for BCD to Excess-3 Code
Converter
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Maps for BCD to Excess-3 Code
Converter
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Department of Electronic Engineering, FJU
Chapter 5 Synchronous Sequential Logic
Code Conversion
 The expressions obtained may be manipulated
algebraically for the purpose of using common gates
for 2 or more outputs.
w = A + BC + BD = A + B(C + D)
x = B’C + B’D + BC’D’ = B’(C + D) + B(C + D)’
y = CD + C’D’ = CD + (C + D)’
z = D’
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Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Binary Adder
 Iterative Logic Array (ILA)
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Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Binary subtractor
 Iterative Logic Array (ILA)
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Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
4-Bit Adder Subtractor
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‫طراحي مدار جمع‌كنندة ‪BCD‬‬
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‫‪Department of Electronic Engineering, FJU‬‬
‫‪ ‬ههت ي ت‪ BCD‬ي عثرتمهكنت كوت ‪ 9‬شي‪ .‬ت هضت تنكد تهدهت ت ه دهت د ت‪ 9‬شدنيت‬
‫ت يوتنقليت زتمه لةتمبلتهاتم ج ت شي‪،‬ت زاگترتنت ي ت صدلت اتره يديتمي‌ت نديت‬
‫‪ 9+9+1=19‬شديتعد تمي‌تد رتصنده ت د تتدكت دي ت‪ BCD‬چهد اتاميدوت تتدكت يدوتنقلدديت‬
‫نه يلت ‪.‬‬
‫‪Chapter 4 Combinational Logic‬‬
‫‪ ‬مددي است كددوتع د ت ت ددي ت‪ BCD‬ا تبعن د رت ا سترفته و د ت تمنه د تصور د تا ت د ا ت‬
‫تكت ي ت‪ BCD‬چه ات يو‪،‬تههه هت تتكت يوتنقليتت لييتمي‌عني‪.‬‬
‫‪ ‬زتصنن تع تههت ي ت‪ BCD‬زت‪ 0‬ت ت‪ 9‬مي‌ شيت ليت ا ستچهد اتامدات كدو‪،‬تشدلت لدوت‬
‫ال كوف هت ج ت ا تع تبعن رت ال تبي‌تف ت اتنظهتگه و تمي‌ش ني‪.‬‬
‫‪BCD Adder‬‬
‫‪‬ک مپی تهه ‌ م شیر س بر هلی‬
‫كیسوا ي هيهی نن م میيهني‬
‫‪ ‬ن ه ین جهع کننيه ه یي ي ا اكیسوا هيهی‬
‫پفیهني ‌ نتین ا ‌ا ههیر کي تح یل هني‪.‬‬
‫‪‬جهع کننيه هيهی چه ‌ا یو ه ی کي که ر ‌‬
‫هه ي نی ‌ز ا‬
‫‌ یک اما نقلی ا ی ‌ یک اما نقلی ره يی ن ه ین ‪9‬‬
‫ا ی ‪ 5‬ره يی ر هي شو‪.‬‬
‫معوبر كو‬
‫غیر ‌‬
‫‪‬کي یک اما هيهی ‪ 4‬یتی ا ی ‪ 6‬لو ‌‬
‫ن ه ین تعي ی ‌ز تهکیبر ی ا ی لو بی ههیو هستني‪.‬‬
‫مح كب تی ا مسوقیه ‌ا‬
‫‪Department of Electronic Engineering, FJU‬‬
‫‪Chapter 4 Combinational Logic‬‬
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‫‪BCD Adder‬‬
‫یشتر ز ‪ 9‬نیسو لف منه‬
‫‌‬
‫هه ا ی‬
‫‪ ‬چ ر‌ مقي ‌ا اما ‌‬
‫یشتر ز ‪ 1+9+9‬شي‬
‫‌‬
‫گتر ز ‪ 9‬هستني ا ی اما نقلی ‪ 1‬هستني‪.‬‬
‫‪‌ ‬ا جهع ‪ BCD‬ي ی ک زا ‌‬
‫ی‬
‫ي ینر ‌‬
‫‪ ‬هه نط ا‌ ک ‌ا جي ‌ل صفح بعي مشخص كو منه‬
‫یشتر ز ‪ 9‬شي‬
‫‌‬
‫كو ک صلجع‬
‫‪ BCD‬تنر زم نی موف‬
‫‪ ‬اص اتی ک خ هیا كوف ه ‌ز جهع کنني ه‬
‫یی جهع کنني ‪ BCD‬ا‬
‫ي ‪6‬ت‬
‫طه حی کنیا یي ا لیوک ج بر موف تني صلجهع‬
‫یی ا‬
‫ا ‪ BCD‬م میيهي‪.‬‬
‫جهع کنیا صلجهع صحیح ا‬
‫‪ ‬ل ه ی ینک تشخیص هیا چ زم نی ین جهع یي نن م ش طبق‬
‫جي ‌ل متی ک یکی ‌ز شه یط ز ‌یه همه ‌ا شي‪:‬‬
‫یی ا ی اما نقلی شي‬
‫‪ ‬ی جهع‬
‫‪ ‬ی ‪ Z4 Z8‬ت م ‪ 1‬شني‬
‫‪ 25‬ی ‪ Z2 Z8‬ت م ‪ 1‬شني‬
‫ره جیر نیهو نيت‬
‫‪Department of Electronic Engineering, FJU‬‬
‫‪Chapter 4 Combinational Logic‬‬
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Binary Multiplier
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Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Binary Multiplier
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Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Binary Multiplier
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Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
4-Bit by 3-Bit Binary Multiplier
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Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Decoder
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Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Decoder
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)‫دياگرام منطقي (موازي و خروجي هاي فعال باال‬
E A B
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Truth Table
m0 m1 m2 m3
B
1 0 0
1 0 0 0
1 0 1
0 1 0 0
1 1 0
0 0 1 0
1
0 0 0 1
1 1
× ×0
m0= AB
A
m1= AB
m2= AB
0 0 0 0
m3= AB
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
)‫دياگرام منطقي (موازي و خروجي هاي فعال پايين‬
B
m0
A
m1
m2
m3
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
2-to-4-Line Decoder with Enable Input
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Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
4 16 Decoder Constructed with Two 3
 8 Decoders
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‫پياده‌سازي توابع بولي با استفاده از ديكدر‬
‫‪ ‬ه ستتبيتلتههتتد بعت د ا تمنهد تجهدال تمدي‌نيهاتا شده ستموفد تيت زتجهلد جدي لت‬
‫ك ان ت ج ت ا ‪.‬‬
‫‪ ‬زتتهعيبتتكت تكيات تتكتگيوت‪ OR‬مي‌ت رتههتت بعيتا تك رو‪.‬‬
‫‪Department of Electronic Engineering, FJU‬‬
‫‪ ‬ههتت بعت ليتا تمي‌ت رت‬
‫ا تمنه عيت زتجهال تمي‌نيهاتنش رت ‪.‬‬
‫‪Chapter 4 Combinational Logic‬‬
‫‪ ‬تكياه ت ات معتته ميتجهال تمي‌نيهاتا تت لييتمي‌عنني‪.‬‬
‫پياده‌سازي تمام جمع‌كننده با ديكدر‬
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
:‫ا طتمهب طت تته مجهععننيه‬
C=x′yz+ x′yz′+xy′z′+xyz
S=xy+xz+yz
S(x,y,z)=∑(1,2,4,7)
C(x,y,z)= ∑(3,5,6,7,)
‫انكودر يا رمز‌كننده‬
‫‪ ‬مي است تنيو ليت كوتع ت ي عثرت‪ 2n‬ا ست ت‪ n‬رطتره ييت ا ‪ .‬اتره ييتعيت‬
‫ييتمون ظهت تمقي ات ا ستت لييتمي‌ش ‪.‬‬
‫‪ ‬ت كوف هت زتچنيتگيوت‪ OR‬ه توتك رو تمي‌ش ‪.‬‬
‫‪Department of Electronic Engineering, FJU‬‬
‫‪ ‬هلتصرت ميق ت ه كست تكيات كو‪.‬‬
‫‪Chapter 4 Combinational Logic‬‬
‫ً‬
‫مثال‪:‬‬
‫يك اينكدر براي براي چهار خط ورودي طراحي كنيد بشرطي كه در هر لحظه از زمان‬
‫فقط يك ورودي فعال باشد‪.‬‬
‫‪A1‬‬
‫‪Encoder‬‬
‫‪Department of Electronic Engineering, FJU‬‬
‫‪A0‬‬
‫‪2-to–4‬‬
‫‪x1‬‬
‫‪x2‬‬
‫‪x3‬‬
‫‪Chapter 4 Combinational Logic‬‬
‫‪x0‬‬
x3 x2 x1 x0
A1
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
d
A1= X2+X3
1
d
1
A1 A0
0
0
0
0
d
d
0
0
0
1
0
0
0
0
1
0
0
1
0
d
d
d
0
0
1
1
d
d
d
d
d
d
0
1
0
0
1
0
0
1
0
1
d
d
0
d
0
1
1
0
d
d
0
1
1
1
d
d
1
0
0
0
1
1
1
0
0
1
d
d
1
0
1
0
d
d
1
0
1
1
d
d
1
1
0
0
d
d
1
1
0
1
d
d
1
1
1
0
d
d
1
1
1
1
d
d
d
d
A0
d
0
0
d
d
d
1
d
A0= X1+X3
d
1
d
d
d
d
d
d
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
‫دياگرام منطقي‬
x1
x3
x2
x0
A0= X1+X3
A1= X2+X3
‫انكودر با حق‌تقدم‬
‫‪ ‬تكتره ييت تگهتهات ه ستمي ات اتنظهتگه و تمي‌ش تع تههيش تمقي اتصرت‪ 1‬كوت‬
‫نزت لتوتع تههةت ا ير ست نك ات ه هت تصفهت شني‪ .‬بعب ا ت تگهت‪ 1‬رتصرت‬
‫نش رت هنيةتمعوبرت رتره ييت نك ات كو‪.‬‬
‫‪Department of Electronic Engineering, FJU‬‬
‫‪ ‬گهت ت ا ستت ت يشترت ط اتههزم رتمس ست ت‪ 1‬ش ني‪،‬ت ا ست ت التهينت قتتقيمت‬
‫هتهستر هيت شو‪.‬‬
‫‪Chapter 4 Combinational Logic‬‬
‫‪ ‬مي اتامزعننيه‌ ست كوتع تش ملتت بعت ق‌تقيمتمي‌ شي‪.‬‬
‫انكودر ‪ 4‬ورودي با حق‌تقدم‬
‫‪ ‬مي ات ا ستچه ات ا ست تك تره ييت كو‪.‬‬
‫‪ ‬جي لت اكتوت‬
‫ا تزيهت كو‪:‬‬
‫‪Department of Electronic Engineering, FJU‬‬
‫ً‬
‫‪ ‬التهينت ق‌تقيمتموعلقت ت‪ D3‬تكپست تتهتيبت ت‪، D2‬ت‪ D1‬تور تو ت‪D0‬ت‬
‫م ‌ي شي‪.‬‬
‫‪Chapter 4 Combinational Logic‬‬
‫‪ ‬گهتههةت ا ير ت ه هت تصفهت شني‪،‬تره ييت‪ V‬تيت ه هت تصفهت شيت اتغیرت‬
‫تن ا ت ه هت ت‪ 1‬ر هيت ‪.‬‬
‫جدول درستي براي انكودر با حق تقدم‬
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
‫ا ير‬
‫ره ييه‬
D0
D1
D2
D3
x
y
V
0
0
0
0
X
X
0
1
0
0
0
0
0
1
X
1
0
0
0
1
1
X
X
1
0
1
0
1
X
X
X
1
1
1
1
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
‫ انكودر‬x‫جدول كارنو براي خروجي‬
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
‫ انكودر‬y‌‫جدول كارنو براي خروجي‬
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
‫مدار انكودر با حق تقدم‬
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
1 ‫ به‬2 MUX ‫يك‬
.‫ نیزت ترطت ا ستهستني‬I2‫ ت‬I1 .‫ هه رت ا ست نوخ بت كو‬S‫ منظ ات زت‬
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
)1 ‫ به‬4( MUX ‫مدار داخلي‬
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
‫ خطي‬1 ‫ خطي به‬2 ‫ چهارتايي‬MUX
‫روشهاي پياده‌سازي يك تابع بولي‬
‫‪ ‬ت كوف هت زت‪PLA‬‬
‫‪Department of Electronic Engineering, FJU‬‬
‫‪ ‬ت كوف هت زتمي اه ست‪ MSI‬ت‪LSI‬‬
‫‪ ‬ت كوف هت زت تكيا‬
‫‪ ‬ت كوف هت زتم لتو‌رلكسه‬
‫‪Chapter 4 Combinational Logic‬‬
‫‪ ‬ت كوف هت زتگيو‌ه ستمنطقي‬
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Boolean Function Implementation
52
‫پياده‌سازي تابع بولي بوسيلة ‪MUX‬‬
‫‪ ‬ك ه‌تهت تنسوتع ت لیرتت تصرهينتموغیرتا تبعن رتموغیرتمنفه ت نوخ بتعه ه‪،‬ت قيةت‬
‫موغیره تا ت ت ا س‌ه ست نوخ بت ‪ MUX‬يهيا‪.‬‬
‫‪Department of Electronic Engineering, FJU‬‬
‫‪ ‬گهت‪ A‬موغیرتمنفه ت( قي‌م نيه) ت بعت ليت شي‪،‬ت ا س‌ه ست‪ MUX‬مي‌ت ننيت‪،A‬ت‪،A′‬ت‬
‫‪ 1‬تت ت‪ 0‬شني‪.‬‬
‫‪Chapter 4 Combinational Logic‬‬
‫‪ ‬گهتت بعت ليت ا ست‪ n+1‬موغیرت شي‪،‬ت‪n‬ت ت زتصور تا ت ترط طت نوخ بت‪ MUX‬صلت‬
‫مي‌عنيا‪.‬‬
‫ي‬
‫مراحل پياده‌ساز ‌‬
‫‪Department of Electronic Engineering, FJU‬‬
‫–‬
‫–‬
‫–‬
‫–‬
‫صفهتهستني‪،‬تصنگ هت ا ستمون ظهت زت‪ MUX‬ه هت ت‪ 0‬مه ات هتمي‌ش ‪.‬‬
‫‪ 1‬هستني‪،‬تصنگ هت ا ستمون ظهت زت‪ MUX‬ه هت ت‪ 1‬مه ات هتمي‌ش ‪.‬‬
‫مق تهتموغیرتمنفه تهستني‪،‬تصنگ هتهه رتموغیرتمنفه ت ت ا ستمون ظهت زت‪ MUX‬هتمي‌ش ‪.‬‬
‫مكهلتمق تهتموغیرتمنفه تهستني‪،‬تصنگ هتمكهلتموغیرتمنفه ت ت ا ستمون ظهت زت‪ MUX‬هت‬
‫مي‌ش ‪.‬‬
‫‪Chapter 4 Combinational Logic‬‬
‫‪ ‬صرهينتموغیرتا تجي تعه ه‪،‬ت قي تا تتهتيبت ت ا ير ست نوخ بت‪ MUX‬صلتعنيي‪.‬‬
‫‪ ‬جي لت اكتوتت بعتا تتشكيلت هيي‪.‬‬
‫‪ ‬محو ستجي لت اكتوتا ت زت الت تكطه‪،‬ت تكطهتجي تعنيي‪.‬‬
‫‪ ‬ه ستمسهتر ستجي تشيه‪،‬ت گهتههت تمقي اتت بعت ه هت ‪:‬‬
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
‫مثال‬
‫ نش رت هت‬MUX‫ جي لت اكتوتت بعت ليتزيهتههه هت تنح ة‌ري ه‌ك زستصرتت كطت‬
:‫شيهت كو‬
‫مثال‬
‫‪Department of Electronic Engineering, FJU‬‬
‫‪Chapter 4 Combinational Logic‬‬
‫‪ ‬جي لت اكتوتت بعت ليتچه اتموغیرهتزيهتههه هت تنح ة‌ري ه‌ك زستصرتت كطت‪MUX‬‬
‫نش رت هتشيهت كو‪:‬‬
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
: 1‫مثال‬
m(1, 2 , 3 , 5 ,6)
a b c
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
F(A , B ,C) = ∑
F
0 0 0
0
0 0 1
1
0 1 0
1
0 1 1
1
1 0 0
0
1 0 1
1
1 1 0
1
1 1 1
0
0
1
1
1
0
1
1
0
I0
I1
I2
I3
I4
MUX
1×8
I5
I6
I7
a b
c
F
: 2‫مثال‬
M(1 ,2 , 3, 6)
a b c
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
F(A , B ,C) = ∑
I0
I1
I2
I3
F
0 0 0
0
0 0 1
1
0 1 0
1
0 1 1
1
1 0 0
0
1 0 1
0
1 1 0
1 c
1 1 1
0
c
I0
1
I1
0
I2
MUX
1×4
I3
a
b
: 3‫مثال‬
m(1, 2 , 4 , 5 ,6)
a b c
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
F(A , B ,C) = ∑
F
0
0 0 0
I0
I1
0 0 1
1
0 1 0
1
0 1 1
0
1 0 0
1
1 0 1
1
1 1 0
1
1 1 1
b c
a
I0= b
c
00
01 11
10
0
1
1
I0
1
1 1
1
I1
I0
MUX
I1= b + c = bc
b
c
1×2
I1
s0
0
a
F
a
b c
: 4‫مثال‬
d
F(A , B , C , D) =∑m(1 , 3 , 5 , 6 , 7 , 10 , 11 , 15)
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
I0
I1
I2
I3
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
1
c d
a b
0
1
0
0
1
00
0
1
0
1
1
01
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
0
00
01
11
1
1
1
10
1
11
1
10
1
I0
1
I2
1
I0=d
I1= d+c
I2=C
1
I1
I3= cd
I3
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
: 4‫مثال‬
d
I0
c
I1
I2
MUX
F
1×4
I3
a
b
64
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Multiplexers with Three-State Gates
65
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Three-State Gates
66
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
2-to-1-Line Multiplexer
67
Department of Electronic Engineering, FJU
Chapter 4 Combinational Logic
Stimulus and Design Modules Interacion
68