RAM-BIST-BISD-jfli

Download Report

Transcript RAM-BIST-BISD-jfli

Built-In Self-Test/Self-Diagnosis
for RAMs
Jin-Fu Li
Advanced Reliable Systems (ARES) Lab.
Department of Electrical Engineering
National Central University
Jhongli, Taiwan
Outline
 Introduction
 Fault Models and Test Algorithms
 Fault models
 Test Algorithms
 Memory BIST/BISD Design
 BIST Design
 BISD Design
 Memory Diagnosis
 Fault Diagnosis
 Defect Diagnosis
Jin-Fu Li
ARES Lab. EE, NCU
2
Introduction
 Modern system-on-chip (SOC) designs typically
consist of hundreds of memories
 Memories usually dominate the chip area
 Furthermore, memories are designed with the
aggressive design rules such that they are prone
to defects
 Thus the memory yield heavily impacts the SOC
yield
 Increasing memory yield can significantly increase
the SOC yield
 Yield-enhancement techniques for memories
 Diagnosis & repair
Jin-Fu Li
ARES Lab. EE, NCU
3
SOC Yield
 Yield of an SOC
 YS  YM  YL
 Improve the yields of memories can drastically increase
the yields of SOCs
 For example, UltraSparc chip yield
Source: R. Rajsuman, IEEE
D&T, 2001
Jin-Fu Li
ARES Lab. EE, NCU
4
Yield Learning Curve
Yield
Diagnosis/repair
Repair
Mature
phase
Early
phase
Intermediate
phase
Jin-Fu Li
ARES Lab. EE, NCU
Time
5
Testing and Repair of RAMs in SOCs
16-core SPARC (Oracle)
DFT features:
1. Scan test + test
compression
2. Programmable memory
built-in self-test (MBIST)
+ repair
3. SerDes internal and
external look-back tests
Jin-Fu Li
ARES Lab. EE, NCU
Niagara2 (Sun)
DFT features:
1.32 Scans + ATPG
2.BIST for arrays
3.….
POWER6 (IBM)
DFT features:
1.Logic BIST
2.BIST for arrays
3.BISR for arrays
4.…
6
Fault Models and Test Algorithms
Conclusions
 Undoubtedly, 3D RAM will be one pioneer
product using 3D integration technology
 Some differences exist between a 2D RAM and a
3D RAM with TSVs
 Those differences incur some challenges on the
testing and repair of 3D RAMs
 Effective testing and repair techniques thus are
imperative for the production of 3D RAMs
 Due to the uncertainty of a 3D RAM
 DFT/DFY/DFR techniques with the feature of
adaptability is one main trend
Jin-Fu Li
ARES Lab. EE, NCU
8