Transcript Seminar on 20the bistdr memory

THE DESIGN OF THE MEMORY BUILT-IN
SELF-TEST, DIAGNOSIS AND REPAIR
(MBISTDR) FOR SRAMs
By
WAN ZUHA WAN HASAN (UPM)
DEPARTMENT OF ELECTRICAL, ELECTRONIC AND
SYSTEM,
FACULTY OF ENGINEERING
UKM
Supervised by
PROF DR MASURI OTHMAN
(UKM)
Co-supervisor
DR BAMBANG SUNARYO SUPARJO
(MENTOR GRAPHIC USA)
Outline
• Introduction
• Memory Architecture
• Memory Fault Models
• Test Algorithms
• Memory Testing, Diagnosis and
Repair
• Conclusion
Introduction
Why BIST, BISD and BISR
The advances of semiconductor
memory technologies have become
more
complex
and
also
the
numbers of memory cell per chip
(transistors) rapidly increase.
The ITRS 2003 has shown an ever
Increasing percentage of chip area
devoted to embedded memory, with
today’s SoCs already consisting of
over 50% memory.
Introduction
Introduction
Memory Sizes Versus Yield
Introduction
ITRS 2004 - SOC Test Requirements
Introduction
The Requirement of Future
MBISTDR
• Fault Modeling – New Fault Models
(defect in deep-submicron)
• Test algorithm design – Optimal
test/diagnosis (high defect coverage)
• BIST – allow at speed testing
• BISR – low cost repair scheme
( improve the yield and reliability)
Memory architecture
Functional RAM Model
Source: Testing and semiconductor memories, A.J. van de Goor
Memory architecture
Reduced Functional RAM Model
Source: Testing and semiconductor memories, A.J. van de Goor
Memory Fault Models
Source: Testing and semiconductor memories, A.J. van de Goor
Memory Fault Models
Source: Testing and semiconductor memories, A.J. van de Goor
Memory Fault Models
Memory Fault Models
Memory Fault Models
Memory Fault Models
Coupling Fault(CF)
Memory Fault Models
Two Cell Faults - cont
Memory Fault Models
Memory Fault Models
Memory Fault Models
Coupling Fault
State Coupling Fault
Source: Testing and semiconductor memories, A.J. van de Goor
Memory Fault Models
Memory Fault Models
Memory Fault Models
Test Algorithms
Functional RAM Testing
•
Traditional Test
- Zero-One - SAF
- Checkerboard - SAF
- GALPAT and Walking 1/0 – AF,
SAF, TF and CF - testing time
unacceptable
- Sliding Diagonal – SAF, TF
- Butterfly – SAF, AF
Source: Testing and semiconductor memories, A.J. van de Goor
Test Algorithms
March Test Algorithms
Test Algorithms
March Test Algorithms
Test Algorithms
March Test Notation
Source: Testing and semiconductor memories, A.J. van de Goor
Test Algorithms
March Test Notation
Source: Testing and semiconductor memories, A.J. van de Goor
Test Algorithms
Source: Testing and semiconductor memories, A.J. van de Goor
Test Algorithms
Comparison of March Tests
March
Test
Algorithm
Number
Operation
Fault Coverage
Test-US
MATS
4n or * 2N
SAF, some AF
MATS+ 2
5n or 5 *
2N
SAF, AF
Test-UT
MATS++
7 or 7 * 2N
SAF, TF, AF
Test-UC
March C
11n
SAF, TF, AF, CF
Test-LC
March A
15n
SAF, AF, CF
Test-LCT
March B
17n
SAF, AF, CF, TF
Source: Testing and semiconductor memories, A.J. van de Goor
Test Algorithms
Fault detection using March CM0
M1
M2
M3
{⇕(w0);  (r0, w1);  (r1, w0);  (r0,w1);
M4
M5
 (r1, w0); ⇕(r0} - 10N Test algorithm
Disable RAM (wait) { (r0, w1,); Disable
RAM(wait)  (r1):} - Data retention fault(DRF)
Test Algorithms
Fault detection using
Extended March C- (covered SOF)
M0
M1
M2
M3
{⇕(w0);  (r0, w1,r1);  (r1, w0);  (r0,w1);
M4
M5
 (r1, w0); ⇕(r0)} - 11N Test algorithm
Disable RAM (wait) { (r0, w1,); Disable
RAM(wait)  (r1):} - Data retention fault(DRF)
Test Algorithms
Fault detection using extended March CMarch Elements
Fault
M0
M1
M2
M3
M4
M5
⇕(w0)
(r0, w1,r1)
(r1, w0)
(r0,w1)
(r1, w0)
⇕(r0)
r0 – s-a-1
r1 – s-a-0
SAF
TF
CF
AF
SOF
DRF
I
N
I
T
I
A
L
Z
A
T
I
O
N
M1(r0,w1) followed
by M2(r1) for </0>
M2(r1,w0) followed
by M3(r0) for </1>
M1(r0,w1)
for Cfid
</1>
*j<i
M1 followed
by M2 for
Cfin </↕>
M2(r1,w0
) for Cfid
</0>
*j<i
M2(r1,w0
) for Cfin
</↕>
*j>i
*j>i
M3(r0,w1) followed
by M4(r1,w0)
Cfid </0>
M1 & M3(r0,w1)
Followed by
M4(r1,w0) for
Cfin </↕>
*all CFids is j<i
M4(r1,w0) followed
by M5(r0) for Cfid for
</1>
M2 & M4(r1,w0)
followed by M5(r0)
for Cfin </ ↕ >
( for j>i is similar)
(M1(r0, w1,r1) M2(r1, w0)) – j>i, (M3(r0,w1) M4 (r1, w0)) – i>j
(Satisfied with known technology)
r1
Disable RAM (wait) { (r0, w1,); Disable RAM(wait)  (r1):}
Test Algorithms
Functional Fault Models for Diagnosis
ICCAD 2000 Chi-Feng Wu
Test Algorithms
Fault detection and diagnosis using
March CL
{(w0);  (r0, w1,);  (r1, w0,); ⇕(r1);
R0
R1
 (r0,w1); ⇕(r1); (r1, w0); ⇕(r0)}
R3
R4
R5
R2
R6
-12N Test algorithm
Disable RAM (wait){ (r0, w1,); Disable RAM(wait) 
(r1):} - Data retention Fault(DRF).
Test Algorithms
Fault detection and diagnosis by
Extended March CL
{(w0);  (r0, w1, r1);  (r1, w0); ⇕(r1); 
R0
R1
R2
(r0,w1); ⇕(r1); (r1, w0); ⇕(r0)}
R4
R5
R6
R3
R7
-13N Test algorithm
Disable RAM (wait){ (r0, w1,); Disable
RAM(wait)  (r1):}- Data retention Fault(DRF).
Test Algorithms
Fault syndrome for March CL
Test Algorithms
Fault syndrome for Extended March CL
Test Algorithms
Existing March Test Algorithms
1. { (w0); (r0, w1,); (r1, w0); (r0,w1); (r1, w0) }Disable RAM (wait){(r0,w1,); Disable RAM(wait) (r1):}
9N test algorithm with data retention test – Rob
Dekker 1988, has covered 100% coverage of the
faults under the listed fault models.
2. { (w0); (r0, w1, r1, w0); delay (r0, r0); (w1); (r1,
w0, r0, w1); delay (r1, r1)}
14N test algorithm
- Said Hamdioui 2000, has
covered 100% coverage of the faults under the listed
fault models and spot defects.
Test Algorithms
Existing March Test Algorithms
3. { (w0); (r0); delay (r0); (w1); (r1); delay (r1)} or
{ (w0); (r0); delay (r0); (w1); (r1); delay (r1)}
6N test algorithm – Baosheng Wang 2003, has reduced
less than half of the required time for the 9N test
algorithm
4. { ⇕(w0); (r0, w1,); ⇕(r1); (r1, w0); ⇕(r0); (r0, w1); ⇕(r1);
(r1, w0); ⇕(r0);
13N test algorithm – V. N. Yarmolik 1996, has
introduced diagnosis capability and achieved 63.6%
diagnostic resolution (SAF & CF).
Test Algorithms
Existing March Test Algorithms
5. { ⇕(w0); (r0, w1,r1, w0); (r0, w1); (r1, w0,r0, w1);
⇕(r1); (r1, w0); ⇕(r0); (r0, w1); ⇕(r1);
18N test algorithm – V. N. Yarmolik 1996, has been
introduced for the diagnosis capability and achieved
90.9%diagnostic resolution (SAF & CF).
6. { (w0); (r0, w1, w0, w1); (r1, w0, r0, w1);  (r1, w0, w1,
w0);  (r0, w1, r1, w0); Hold  (r0, w1); Hold  (r1);
20N test algorithm – I. Kim 1998, has been diagnosis
capability and achieved 59% diagnostic resolution (SAF
& CF).
Test Algorithms
Existing March Test Algorithms
7. { (w0); (r0, w1,r1, w0 ); ⇕(r0); ⇕(w1); (r1, w0,r0, w1);
⇕(r1); }
12N test algorithm – T. J. Bergfeld 2000, has
proposed diagnosis capability but it could only achieve
22.7% diagnostic resolution (SAF & CF).
8. { ⇕(w0); (r0, w1, r1); ⇕(r1); (r1, w0,r0); ⇕(r0); (r0, w1,
r1); ⇕(r1); (r1, w0, r0); ⇕(r0); }
17N test algorithm – Jin-Fu Li 1996, has introduced
diagnosis capability and achieved 100% diagnostic
resolution(SAF & CF).
Test Algorithms
Existing March Test Algorithms
9. {(w0); (r0, w1,); ⇕(r1); (r1, w0); (r0, w1); ⇕(r1);
(r1, w0); ⇕(r0);}
12N test algorithm plus 3N or 4N ( for aggressor
locating) – V. A. Vardanian 2002, has introduced
diagnosis capability and achieved 100%
diagnostic resolution.
Test Algorithms
STATE-OF-ART FOR TEST ALGORITHMS
• Optimality in term of time complexity
• Regularity and symmetry such that the
self-test circuit can minimize the silicon
area
• High defect coverage and diagnosis
capability in order to increase the repair
capabilities and the overall yield
Memory Testing, Diagnosis and Repair
MBIST ARCHITECTURE
BIST
CONTROLLER
FSM
COMPARATOR
SRAM
MBIST
SYSTEM
Memory Testing, Diagnosis and Repair
MBISTD ARCHITECTURE
BIST
CONTROLLER
FSM
COMPARATOR
INDICATOR
SRAM
MBISTD
SYSTEM
Memory Testing, Diagnosis and Repair
BISTD
STATE-OF-ART FOR BISTD
• Minimizing BIST overhead in both silicon
area and routing
• Supporting diagnosis capabilities
• Supporting different kinds of memories
(single-port, multi-port)
Memory Testing, Diagnosis and Repair
MBISTDR ARCHITECTURE
BIST
CONTROLLER
FSM
COMPARATOR
INDICATOR
SRAM
EXTRA COLUMN
/ROW/WORD
MBISTDR
SYSTEM
Conclusion
MBISTDR is essential
for
reliability in the near future.
memory
The addition of BISD and BISR will
enhance the yields of overall memory
chips.
New test algorithm and fault syndromes
base on March CL has been proposed to
detect and diagnose SOF and AF.
THANK YOU
Q&A
THANK YOU
Q&A
THANK YOU
Q&A
Memory Testing, Diagnosis and Repair
Example of MBISR
Data
Address
Control
MBIST
Mux
Fuse Box
Redundancy
Logic
RAM
Mux
Data
The Memory BIST and Self-Repair (MBISR) Concept [Volker 2001].
Memory Testing, Diagnosis and Repair
• The Figure above shows the MBIST
and Self-Repair using redundancy
logic and Fuse Box concept.
• The MBISR concept contains an
interface
between
MBIST
logic,
redundancy wrapper logic to replace
defect address and Fuse boxes to
store the failling addresses
On Going Research
The
design
MBISTDR .
and
simulation
of
New Test Algorithms with Diagnosis
capability will be designed according
to the required coverage and testing
time.
MBISTDR Methodology
d_in
addr
5
bistr_data_write
12
12
MUX_1
bistr_en
clk
mode_sel
5
Bistr_error_addr
5
Bistr_add
r
Wr_en
MBISTDR
CONTROLLER
12
32 X 12
SRAM
Rd_en
Sram_error
12
Mode_sel
MUX_2
bistr_data_read
5
12
d_out
Design of MBISTDR Controller for Stuck-at Faults
MBISTDR Methodology
The schematic of MBISTDR Controller for Stuck-at
Faults
MBISTDR Methodology
Figure above shows that MBISTDR
contains MBISTDR controller and 32x12
SRAM
Test Pattern In – Bistr_data_write (w0/w1)
Mode_sel – test or normal mode Enable
the Wr_en or Rd_en
Test Pattern Out – Bistr_data_read(r0/r1)
MBISTDR Methodology
Test and Repair Algorithm of MBISTDR
controller for Stuck-at Faults
MBISTDR Methodology
Figure above Shows that, how MBISTR
controller implements the test and repair
algorithm to the 32x12 SRAM memory.
Procedure:
address 1 – w0 then compare with r0
address 2 – w1 then compare with r1
Run until either marked addresses or
memory addresses reach the maximum
MBISTDR Results And
Discussion
Fault Free Results for MBISTDR During Normal
mode Operation
MBISTDR Result And Discussion
Fault Detection Results for MBISTDR during Test
mode Operation
MBISTDR Result And Discussion
Results for MBISTDR During Normal Mode and Test
Mode Operation
Final Target for MBISTDR
Criteria:
TA
1)High
defect
coverage
and
diagnosis
capability in order to increase the repair
capabilities and the overall yield – below 17N
BISTDR
1)Supporting diagnosis capabilities – 100%
diagnosis resolution (include SOF and AF)
2) Using Extra Memory for the BISR
MBISTDR Conclusion
A new memory Built-in Self-test and
Repair concept has been designed and
this concept is proposed without
using any extra rows and columns.
These test and repair are only focused
on the reconfiguration of the memory
addresses, which means no extra
spaces needed as the previous
researches.