Transcript Hierarchical, Physical-Aware, Built-In Self-Repair of

Hierarchical, physical-aware, built-in
self-repair of embedded memories
V.R. Devanathan, Harsharaj Ellur, Mohd. Imran, Shivani Bathla
Texas Instruments India Pvt. Ltd.
{vrd, harsharaj.ellur, m-beg, shivani}@ti.com
1
Motivation
 Need area efficient memory test/repair flow over native
EDA solution, with support for incremental repair
■ Total test and repair area overhead as high as 1M gate!
Area overhead
600
BIST DP
500
BIRA DP
FuseROM
# gates (K)
400
300
200
100
0
A
[0.5Mb]
B
[0.8 Mb]
C
[6.4 Mb]
D
[8.8 Mb]
IP Cores
E
[10.0 Mb]
F
[45.8 Mb]
2
Optimizing BIST datapath[1]
 Automated, physical-aware grouping to ease congestion
 Timing & interconnect-aware pipelining to ease timing closure
Grp4
Grp4
Grp3Grp3
Grp1
Grp1
Grp5
Grp2
Grp2
Grp5
LEGEND
LEGEND
: Level 0
TIA pipelines
: Level
0 Group
: Level 1
TIA pipelines
: Level
1 Group
: Level 2
TIA pipelines
: Level
2 Group
Pipelines assigned
on each
data-path
Physical-aware
grouping
of clusters
branch using TIA heuristics
[1] V. R. Devanathan, et. al., “Novel approaches for effective and optimized memory test flow in nanoscale technologies”, VTS 2012
3
Optimizing BIRA datapath
 Physical-aware sharing of BIRA across multiple memories
■ Group temporally separated memories, with similar repair code
 Timing and interconnect-aware BIRA data-path pipelining
Grp4
Grp3
Grp1
BIRA
Grp2 Grp3
BIRA
Grp1
Grp1
BIRAGrp4
BIRA
Grp2
Grp3
BIRA
BIRA
BIRABIRA execution
BIRA on Grp2
Grp1
Grp5
BIRA
Grp4
BIRA
BIRA execution on Grp3
Grp5
Grp2
Grp2
BIRA
Grp4
Grp3
BIRA
BIRA
BIRA architecture
Grp1
overview
Grp5
Grp2
Grp3
BIRA
BIRA
Grp4
BIRA
BIRA data-path
grouping overview
Grp5
BIRA
BIRA execution on Grp4
Grp5
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Proposed self-repair execution flow
BISoR + BIRA
FDI
FDO
FDI
M1
FDO
M2
FDI
FDO
FDI
FDO
FDI
FDO
FDI
FDO
M3
M4
M5
M6
MemGrp1
MemGrp2
EFUSE
FuseROM
PBIST
Hard-repair
Soft-repair
Test group
group
on2
1SoC
1
2
5
Optimizing Fuse ROM storage
 Dynamic re-configuration of memory fuse chain
■ Store only repaired memory data in FuseROM
 Support for incremental repair with intelligent bypass wrappers
INCREMENTAL
REPAIR
ON MEM1
&&
MEM3
REPAIRING
MEM0,
MEM2
MEM5
6
Robust repair verification flow
 BIRA & BISoR shared across different memories, with
different configurations.
■ Need fool-proof verification on each memory.
Mem0
Mem0
Mem0
FDI
FDI
FDI
Q
QQ
FDO
FDO
FDO
Soft repair
Run BIST with
self-repair
Repair code
Mem_Q
BIRA
Soft unload
Run BIST postwith
self-repair
PBIST
Per-instance
unique fail
injection
TCL based
fault injection
Expected fuse
register value
TCL based fuse
register
comparator
PASS
BISoR
Verification
Complete
FAIL
Check BISoR
integration /
flow parameters
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Results: BIST and Repair data-path area
 Reduced congestion with proposed BIST/BIRA data-path grouping
 Significant (~6X) area reduction over native EDA solution
PD flylines for level-0 + level-1
datapath routes for a SoC core,
without physical-aware flow
PD flylines for level-0 + level-1
datapath routes for a SoC core,
with the proposed flow
8
Results: FuseROM area
 Significant area reduction without (and with) incremental repair
■ Compaction-based native EDA solution: 2.3X (and ~44%)
■ Proposed dynamic re-configuration: 6.6X (and 4.5X)
 Compaction (native EDA solution) may be used over the
proposed technique for further area reduction
FuseROM area with incremental repair
600
Conventional unoptimized
500
Conventional compacted
#gates (K)
Proposed
400
300
200
100
0
A
B
C
D
Core
E
F
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Conclusion
 A novel self-repair flow is presented, that provides
■ ~6X reduction in data-path area, over native EDA flow
■ ~2.5X reduction in FuseROM area, over native EDA flow
■ Automated, physical-design friendly generation of
structured BISR data-path
■ Incremental repair support
 Proposed flow is vendor-agnostic and pluggable into
vendor EDA BISR solution
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Thank You!
11
Built-In Soft-Repair (BISoR) controller
 Soft-repair triggered by PBIST after test of each group.
■ Each BIRA/BISoR is shared across ‘N’ memory groups.
FDO
FDI
FDI
Repair code
FDI
FDI
FDI
Mem0
Mem0
Mem0
Repair code
QQ
Q
Mem_Q
Fail encode
Mem_ID
BIRA
fclk
Mem_ID
FCLK
FCLK
FCLK
Mem_fclk[N-1:0]
Mem_ID
BISoR
CG
CG
CG
fuse clock leaker
Fuse_length per mem_ID
Trigger
0
Fuse_clk
...
CG Bira_fclk
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Built-in Hard-repair controller
 EFUSE controller enhanced for hard-repair
■ Shift out soft-repaired memory fuse chain, slice data wrt FuseROM
data-width (W), and automatically blow/write data into FuseROM
fdi
M0
M1
Memory Fuse Register Chain
…
M2
MM-2
MM-1
fdo
W
Fuse auto-load
Fuse auto-unload
EFUSE
Fuse ROM
W
Control / reserved bits
…
R
C
13
Support for incremental repair: BISoR
 Minor enhancements to BIRA and BISoR
■ BIRA: Merging of old repair and new repair code
■ BISoR: Increased clock-leaker pulses and additional trigger
BIRA
Merge
FDO
FDI
FDI
FDI
FDI
FDI
Repair code
Mem0
Mem0
Mem0
Merged repair code
QQ
Q
Mem_Q
Mem_ID
Init repair code
Fail encode
fclk
Merge_Trigger
Mem_ID
FCLK
FCLK
FCLK
Mem_fclk[N-1:0]
BISoR
Mem_ID
CG
CG
CG
fuse clock leaker
(2*Fuse_length+1) per mem_ID
Trigger
0
...
CG Bira_fclk
Fuse_clk
Delay (Fuse_length per mem_ID cycles)
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Support for incremental repair: FuseROM
 Bypass wrapper supporting incremental repair
15
Results: BIST and Repair data-path area
 Negligible (~1%) impact to test time with proposed selfrepair flow
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Results: FuseROM area
 Significant area reduction without (and with) incremental repair
■ Compaction-based native EDA solution: 2.3X (and ~44%)
■ Proposed dynamic re-configuration: 6.6X (and 4.5X)
 Compaction (native EDA solution) may be used over the
proposed technique for further area reduction
17