Transcript Feedback.ppt

Feedback:
Principles & Analysis
Dr. John Choma, Jr.
Professor of Electrical Engineering
University of Southern California
Department of Electrical Engineering-Electrophysics
University Park; Mail Code: 0271
Los Angeles, California 90089-0271
213-740-4692 [OFF]
626-915-7503 [HOME]
626-915-0944 [FAX]
[email protected] (E-MAIL)
EE 448
Feedback Principles & Analysis
Fall 2001
Overview Of Lecture
• Feedback
 System Representation
 System Analysis
• High Frequency Dynamics
 Open And Closed Loop Damping Factor
 Open And Closed Loop Undamped Natural Frequency
 Frequency Response
Phase Margin
•
High Speed Transient Dynamics




Step Response
Rise Time
Settling Time
Overshoot
65
Open Loop Model
X(s)
•
Gain:
Aol (s) =
 Parameters
Open Loop
Amplifier:
A ol (s)
Aol (0)
Y(s)
s
1 – z
o
s
s
1 + p
1 + p
1
2
 Aol (0)
 Zero Frequency Gain
 zo
 Frequency Of Zero
 p1
 Frequency Of Dominant Pole
 p2
 Frequency Of Non–Dominant
Pole
 Frequency Of Zero Can Be Positive (RHP Zero) Or
Negative (LHP Zero)
 Note That A Simple Dominant Pole Model Is Not
Exploited
• Input And Output Variables
 Input Voltage Or Current Is X(s)
Output Voltage Or Current Is Y(s)
663
Open Loop Transfer Function
A ol (s) =
•
A ol (0)
s
1 – z
o
s
s
1 + p
1 + p
1
2
Damping Factor:
ol = 1
2
=
s
A ol (0) 1 – z
o
2 ol
s2
1 +
s +
2
 nol
 nol
p2
p1
+
p1
p2

Measure Of Relative Stability
 Measure Of Step Response Overshoot And Settling Time
•
•
nol =
Undamped Natural Frequency:
p1 p2
 Measure Of Steady State Bandwidth
 Measure Of "Ringing" Frequency And Settling Time
Poles
 Dominant Pole Implies ol >> 1
 Complex Poles Imply ol < 1
 Identical Poles Imply  = 1
ol
674
Closed Loop Transfer Function
+
X(s)
–
Open Loop
Amplifier:
A ol (s)
Y(s)
Acl (s) =
Feedback:
Aol (s)
1 + f Aol (s)
T (0) = f Aol (0)
Loop Gain (Return Ratio w/r To Feedback Factor, f ):
T (s) = f A ol (s) =
•
Aol (s)
1 + T (s)
T (s) = f Aol (s)
f
•
=
s
f A ol (0) 1 – z
o
s
s
1 + p
1 + p
1
2
Closed Loop Gain:
A cl (s) =
s
A cl (0) 1 – z
o
2cl
s2
1 +
s +
2
 ncl
 ncl
=
s
T (0) 1 – z
o
2ol
s2
1 +
s +
2
 nol
 nol
Obtained Through Substitution
Of Open Loop Gain Relationship
Into Closed Loop Gain Expression
68
Closed Loop Parameters
s
1 – z
o
s
s
1 + p
1 + p
1
2
A ol (s) =
A ol (0)
T (s) =
s
T (0) 1 – z
o
s
s
1 + p
1 + p
1
2
•
–
2ol
s2
1 +
s +
2
 nol
 nol
s
A cl (0) 1 – z
o
T (0)
1 + T (0)
2cl
s2
1 +
s +
2
 ncl
 ncl
 nol
2zo
T (0)
 ncl = nol
Closed Loop Undamped Frequency:
Aol (0)
"DC" Closed Loop Gain:
Acl (0) =

•
•
ol
1 + T (0)
=
A cl (s) =
Closed Loop Damping Factor:
cl =
s
A ol (0) 1 – z
o
f A ol (0)
1 + T (0)
1 + T (0)
 T(0) Large For Intentional FeedbackA cl (0) 
1
f
 T(0) Possibly Large For Parasitic Feedback
69
Closed Loop General Comments
cl =
•
–
T (0)
1 + T (0)
 nol
2zo
 ncl = nol
1 + T (0)
Damping Factor
 Potential Instability Increases With Diminishing Damping Factor
 Potential Instability Strongly Aggravated By Large Loop Gain

•
ol
1 + T (0)
 Note: Open Loop Damping Attenuation By Factor Of
Square Root Of One Plus "DC" Loop Gain
 For Intentional Feedback Having Closed Loop Gain Of (1/f ),
Worst Case Is Unity Gain (f = 1), Corresponding To Maximal T(0)
Open Loop Zero
 Closed Loop Damping Diminished, Thus Potential Instability
zo > 0
Aggravated, For Right Half Plane Open Loop Zero
 Closed Loop Damping Increased, Thus Potential Instability
Diminished, For Left Half Plane Open Loop Zeroz o < 0
Undamped Frequency
 Measure Of Closed Loop Bandwidth
 Closed Loop Bandwidth Increases By Square Root Of One Plus
"DC" Loop Gain, In Contrast To Increase By One Plus "DC" Loop
Gain Predicted By Dominant Pole Analysis
70
Step Response Example Of Damping Factor Effect
Normalized Response
2.00
1.80
Transmission Zero Assumed To
Lie At Infinitely Large Frequency
0.05
1.60
0.2
1.40
1.20
0.5
1.00
0.8
1
0.80
3
0.60
Damping Factor = 5
0.40
0.20
0.00
0
1
2
3
4
5
6
7
8
9
10
11
Normalized Time
12
13
14
15
16
17
18
19
20
n t
71
Phase Margin
s
T (0) 1 – z
o
T (s) =
s
s
1 + p
1 + p
1
2

–1
 (v ) = – tan
z o – tan
•

p1
–1
– tan
–1

p2
Unity Loop Gain Frequency
 u  T(0) p 1
 Assumes Frequencies Of Zero And Second Pole Are LargerThan
u
kpko – 1
p 2 = k p u
z o = k o u
Substitutions:
k
kp + ko
Phase Margin
 Difference Between Actual Loop Gain Phase Angle And –180;

•
•
Aol (s)
1 + T (s)
Acl (s) =
A Safety Margin For Closed Loop Stability
m
 Approximate Phase Margin:
 tan
–1
1 + k T(0)
T(0) – k
 tan

Sincek o Can Be Negative, k Can Be A Negative Number

Result Is Meaningful Only Fork o

–1
(k)
kp > 1
72
Phase Margin Characteristic
120
Phase Margin (deg.)
100
T(0) = 1
80
T(0) = 5
60
40
20
T(0) = 100
0
-1
-0.8 -0.6 -0.4 -0.2 0
-20
k
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
-40
-60
73
Circuit Response Parameters
s
A cl (0) 1 – z
o
2cl
s2
1 +
s +
2
 ncl
ncl
s
T (0) 1 – z
o
s
s
1 + p
1 + p
1
2
T (s) =
k

A cl (s) =
T(0) p 1 p 2 = k p  u
u 
z o = k o u
kpko – 1
kp + ko
p2
p1
ol = 1
2
 nol =
p1 p2
p1
p2
+
 ncl = nol
1 + T (0)
l Closed Loop Damping Factor:
cl =
1
2
1
k p T(0) 1 –
ko
k p T (0) 1 + T (0)
+ 1


tan
kp
2
1–
1
ko
l Closed Loop Undamped Frequency:
 ncl
= u
k p 1 + T (0)
T(0)
l Phase Margin:  m

tan

–1
u
kp
1 + k T(0)
T(0) – k
–1
(k)
74
Closed Loop Example Calculation
• Given: T(0)
= 25 &
ko = 5
• Desire Maximally Flat Closed Loop Response,

> 1/
Which
cl
Implies
• Computations:
kp
cl 
2

k pk o – 1
kp + ko
k =

•
1–
2
1
ko

m

tan
 k p > 3.125
 k = 1.8
Requisite Phase
k T(0)
–1 1 +Margin:
f
1
2

T(0) – k
 f
m

63.28
 In Practical Electronics, Phase Margins In The 60s Of
Degrees
Are Usually Mandated, Which Requires That The NonDominant
75
Closed Loop Step Response: Problem Formulation
Closed Loop
Amplifier:
A cl (s)
X(s)
= 1/s
Y(s)
= A (s)/s
A cl (s) =
cl
• Problem Setup:
dcl
•

M


 ncl
zo
 ncl
2cl
s2
1 +
s +
2
 ncl
 ncl
(Damped Frequency Of Oscillation
1 – cl2

s
A cl (0) 1 – z
o
ko
kp
Normalized Variables:
x



 (t)
1 –

Y n (s)
y (t)
A cl (0)

yn (t)
(Normalized Time Variable)


ncl t
(Output Normalized To Steady–State Response)
y (t)
A cl (0)
Y (s)
A cl (0)
=
(Error Between Steady State And Actual
Output Responses)
s
1 – z
o
2cl
s2
s 1 +
s +
2
 ncl
 ncl
76
Closed Loop Step Response: Solution
Closed Loop
Amplifier:
A cl (s)
X(s)
= 1/s
Y n (s) =
Y(s)
= A cl (s)/s
s
1 – z
o
2cl
s2
s 1 +
s +
2
 ncl
ncl
y n (t) = 1 –
 (t)
1/2
•
Solution:  (x)
=
M
zo
 ncl

–1
M
 = tan
• Assumptions:

cl < 1

zo + cl  ncl > 0
2
1 –
cl2
2
e – cl x Sin
1 – cl2
x
x


M
1 + 2 M cl + M
ko
kp
+ 
 ncl t
1 – cl2
1 + M cl
(Underdamped Closed Loop Response)
(Satisfied For Right Half Plane Zero)
77
Closed Loop Step Response Example #1
2
Damping Factor = 0.2
M
Q == 11
Normalized Step Response
1.5
0.5
1
0.9
0.5
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
Normalized Time
-0.5
78
Closed Loop Step Response Example #2
1.75
Damping Factor = 0.2
Normalized Step Response
1.5
M
Q == 55
1.25
0.5
1
0.9
0.75
0.5
Note That An Increase In The
Frequency Of The Zero Diminishes
Undershoot But Does Not
Substantially Reduce Overshoot
0.25
0
0
-0.25
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
Normalized Time
79
Closed Loop Settling Time
1/2
 (x)
•
=
M
2
1 –
cl2
e – cl x Sin
x
1 – cl2
+ 
y n (x) =
1 –
 (x)
Observations






•
1 + 2 M cl + M
2
Magnitude Of Error Term Decreases Monotonically With x
Maxima Of Error Determined By Setting Derivative Of Error
Term With Respect To x To Zero
Maxima Are Periodic With Period 
First Maximum Of Error Establishes Undershoot Point
Determine Second Maximum And Constrain To Desired Minimal Error
Procedure
 Letx m Be The Normalized Time Corresponding To Second
Error Maximum
x m To
 Letm Be The Magnitude Of Error Corresponding
xm
 If m Is The Desired Settling Error,
Represents The Settling Time
Of the Circuit
80
Closed Loop Settling Time Results
1/2
 (x)
=
1 + 2 M cl + M
M
2
1 –
2
cl2
e – cl x Sin
y n (x) = 1 –
•
Results:
xm
m
•
1
=
1
=
– cl2
1 – cl2
x
+ 
 (x)
 + tan
2
1 + 2 M cl + M
M
1 – cl2
cl + M
–1
– x
e cl m
For Large M (Far Right Half Plane Zero):
xm
m



1 – cl2
exp – 
2
4 – kp

kp
4 – kp
81
Closed Loop Settling Time Example
•
•
Requirements
 Settling To Within One Percent In 1 nSEC
 Assume Zero Is In Far Right Half Plane (Reasonable
Approximation For Common Gate And Compensated Source
Follower; First Order Approximation For Common Source)
 Assume Very Large "DC" Loop Gain
Computations
 m

exp – 
kp
 0.01  k p > 2.73 ;
4 – kp
Second Pole Must Be At Least 2.7 Times Larger Than
Unity Gain Frequency

x m =  ncl t m 
 ncl 
u
kp
2
4 – kp
= 5.575   ncl  2  (887.2 MHz) ;
  u  2  (537 MHz)
 Required Phase Margin: f
m

tan
–1
(k p ) = 69.9
82