Transcript ppt
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 24: November 4, 2011 Synchronous Circuits 1 Penn ESE370 Fall2011 -- DeHon Today • Clocking – Latches – Registers • Timing discipline 2 Penn ESE370 Fall2011 -- DeHon Clocking Latches, Registers 3 Penn ESE370 Fall2011 -- DeHon Why Clocked Circuits? • Synchronize external events • Reuse logic – FSM – Pipelining • Synchronize internal use of logic 4 Penn ESE370 Fall2011 -- DeHon Challenge • Logic paths have different delays – E.g. different output bits in an adder • Delay of signal data dependent – E.g. length of carry • Delay is chip dependent – E.g. Threshold Variation • Delay is environment dependent – E.g. Temperature 5 Penn ESE370 Fall2011 -- DeHon Challenge • • • • • Logic paths have different delays Delay of signal data dependent Delay is chip dependent Delay is environment dependent Proper behavior depends on inputs being coordinated – Match the inputs that should interact 6 Penn ESE370 Fall2011 -- DeHon Discipline • Add circuit elements to – hold values – and change at coordinated point • Control when changes seen by circuit • Only have to make sure to wait long enough for all results • Decouple – timing of signal change – from timing of signal usage Penn ESE370 Fall2011 -- DeHon 7 Synchronous Discipline • Add state elements (registers, latches) • Compute – From state elements – Through combinational logic – To new values for state elements 8 Penn ESE370 Fall2011 -- DeHon What does this do? 9 Penn ESE370 Fall2011 -- DeHon Latch f=0 Out=In f=1 Out=Out f transitions 01 Out holds value 10 Penn ESE370 Fall2011 -- DeHon Latch • In pass-through mode (f=0), – acts like buffer • In latch mode (f=1), – holds last value given 11 Penn ESE370 Fall2011 -- DeHon Latch • In pass-through mode (f=0), – acts like buffer • In latch mode (f=1), – holds last value given • Timing Requirements? 12 Penn ESE370 Fall2011 -- DeHon Latch Timing • Must present input value sufficiently before the f transitions 01 – Must have time to propagate and charge Out – About how long is that in this case? • Setup Time (tsu) – must setup latch input prior to passhold transition 13 Penn ESE370 Fall2011 -- DeHon Latch Timing • Must not change input before switched over to hold state – How long in this case? – Takes time for inverter to charge before hold path enabled. 14 Penn ESE370 Fall2011 -- DeHon Latch Timing • Must not change input before switched over to hold state • Hold Time (thold)– must hold data input until passhold transition complete 15 Penn ESE370 Fall2011 -- DeHon What happens here? 16 Penn ESE370 Fall2011 -- DeHon Observe • Latch alone – In flow-through mode half of cycle – Can still get flow-through, combinational cycles 17 Penn ESE370 Fall2011 -- DeHon Multiple Latch Discipline • Open latches at disjoint times • At all times one latch on every path is closed 18 Penn ESE370 Fall2011 -- DeHon Register • Two back-to-back latches – Open one latch at a time – Having one of each on every cycle breaks up combinational cycle 19 Penn ESE370 Fall2011 -- DeHon Register • Passhold on input latch samples value • Holdpass on output latch presents stored value to circuit Master and Slave latches 20 Penn ESE370 Fall2011 -- DeHon Register • How long from f0 rise to output? • How long from f1 fall to output – Part of clkoutput (tclk-q) 21 Penn ESE370 Fall2011 -- DeHon Clock Signal • Can we use a single signal for clock? 22 Penn ESE370 Fall2011 -- DeHon Clock Issues • Possible failure modes? – Flow through during transition? – Loading on clock phases – Delay in compute f1? 23 Penn ESE370 Fall2011 -- DeHon What if it’s early? f0 early 24 Penn ESE370 Fall2010 -- DeHon What if it’s late? f0 late 25 Penn ESE370 Fall2011 -- DeHon What does this do? 26 Penn ESE370 Fall2010 -- DeHon What does this do? • Outputs when – Input 0? – Input 1? • Can ever both be on? • What does output waveform look like? 27 Penn ESE370 Fall2010 -- DeHon Clocking Discipline Identify: setup, hold, clk->Q, logic evaluation 28 Penn ESE370 Fall2011 -- DeHon Clocking Discipline 29 Penn ESE370 Fall2011 -- DeHon Clocking Discipline • Follow discipline of combinational logic broken by registers • Compute – From state elements – Through combinational logic – To new values for state elements • As long as clock cycle long enough, – Will get correct behavior 30 Penn ESE370 Fall2011 -- DeHon Next Week • Monday: guest lecturer (andre away) • Tuesday: Andre away (no office hour) • Wednesday: Midterm – No lecture – Midterm 7-9pm in Towne 303 – New Project out • Thursday: <nothing> (read project) • Friday: Class Penn ESE370 Fall2011 -- DeHon 31 Ideas • Synchronize circuits – to external events – disciplined reuse of circuitry • Leads to clocked circuit discipline – Uses state holding element – Prevents • Combinational loops • Timing assumptions • (More) complex reasoning about all possible timings 32 Penn ESE370 Fall2011 -- DeHon