Transcript ppt
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 15: October 14, 2011 Inverter Performance 1 Penn ESE370 Fall2011 -- DeHon Previously • Delay as RC-charging • Transistor – Capacitance – Drive Current – As a function of geometry (W/L) 2 Penn ESE370 Fall2011 -- DeHon Today • Sizing • Large Fanout • Capacitance Revisited – Miller Effect – Parallel Gate Capacitance 3 Penn ESE370 Fall2011 -- DeHon Transistor Sizing • What happens to Ids as a function of W? VDSAT IDS satCOX W VGS VT 2 • What happens to Cg as a function of W? CG CoxWL • Conclude: faster transistors present more load on their inputs Penn ESE370 Fall2011 -- DeHon 4 First Order Delay • R0 = Resistance of minimum size NMOS device • C0 = gate capacitance of minimum size NMOS device • Rdrive = R0/W • Cg = WC0 5 Penn ESE370 Fall2011 -- DeHon t model • All delays are RC delays • Always have an R0C0 term t= R0C0 • Express all delays in t units • Like l units for measurement – Separate delay into • Technology dependent term t= R0C0 • Technology independent term 6 Penn ESE370 Fall2011 -- DeHon Inverter Sizing • What is the impact of the delay on the middle inverter if double size of all the transistors? 7 Penn ESE370 Fall2011 -- DeHon How Size • How size to equal Rise and Fall? mn=500cm2/Vs, mp=200cm2/Vs – When velocity saturated – Rdrive=R0/2 8 Penn ESE370 Fall2011 -- DeHon Worst Case Delay • Largest R • Rdrive = max(Rpullup,Rpulldown) • If equalize Rpullup and Rpulldown – Rdrive = Rpullup=Rpulldown 9 Penn ESE370 Fall2011 -- DeHon Large Fanout • What is delay if must drive fanout=100? 10 Penn ESE370 Fall2011 -- DeHon What Delay? • What is delay here? 11 Penn ESE370 Fall2011 -- DeHon How Size • How size transistors to minimize delay? 12 Penn ESE370 Fall2011 -- DeHon Optimizing • • • • • Delay = 2Wmid/1 + 200/Wmid How minimize? D(Delay)/D(Wmid) = 0 2 – 200/(Wmid)2=0 Wmid=sqrt(100) = 10 13 Penn ESE370 Fall2011 -- DeHon Delay? • Delay at optimal Wmid? 14 Penn ESE370 Fall2011 -- DeHon Try again • What is the delay here? 15 Penn ESE370 Fall2011 -- DeHon …and Again • Delay here? 16 Penn ESE370 Fall2011 -- DeHon Lesson • • • • Don’t drive large fanout with a single stage Must scale up over a number of stages …but not too many Exact number will be technology dependent 17 Penn ESE370 Fall2011 -- DeHon Charge on Capacitors 18 Penn ESE370 Fall2011 -- DeHon Questions • What is DQ when switched? • Equivalent Capacitance? • Contribution from each transistor? 19 Penn ESE370 Fall2011 -- DeHon Gate-Drain Capacitance • What is the voltage across Vin—V2 – When Vin=Vdd – When Vin=Gnd • What is DV across Vin—V2 when Vin switches from Vdd to Gnd? 20 Penn ESE370 Fall2011 -- DeHon Miller Effect • For an inverting gate • Capacitance between input and output must swing 2 Vhigh • Or…acts as doublesized capacitor 21 Penn ESE370 Fall2011 -- DeHon Admin • Drop Date Today • HW5 out 22 Penn ESE370 Fall2011 -- DeHon Ideas • First order delay reason in t=R0C0 units • Scaling everything up doesn’t help • Drive large capacitive loads in stages 23 Penn ESE370 Fall2011 -- DeHon