ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 16: October 12, 2012 Performance: Gates Penn ESE370 Fall2012 -- DeHon.

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Transcript ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 16: October 12, 2012 Performance: Gates Penn ESE370 Fall2012 -- DeHon.

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 16: October 12, 2012
Performance: Gates
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Penn ESE370 Fall2012 -- DeHon
Previously:
First Order Delay
• R0 = Resistance of minimum size
NMOS device
• C0 = gate capacitance of minimum size
NMOS device
• Rdrive = R0/Wn
Cg = WC0
• Technology independent relative delay
t = R0C0
• Large fanout – drive in stages
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Today
• Delay in Gates
• Data Dependent Delay
• Large Fanin
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Gates
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Data Dependent Delay
• Resistance depends on input values
delay depends on input data
t-delays assuming minsize?
assume 2C0 load
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How Size
• How size to equalize worst-case rise/fall
times for Rdrive=R0/2?
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How Size
• How size for equal rise/fall
for Rdrive=R0/2?
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Input Load
• Input capacitance per input in each
case?
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Observe
• Ratio of Input Load Capacitance to
Output Drive Strength: CILoad/Ids
– Differs with gate function
• Some gates give more drive per
capacitive load we pay
– When Ids differ at same W
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How Size
• Size equalize rise/fall
times Rdrive=R0/2?
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Increasing Fanin
• What happens to input capacitance as
fanin (k) increases
– Keeping output drive the same
• E.g. Rdrive=R0/2
• k-input nand gate has what input
capacitance?
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Fanin
• Conclude: gates slow down with fanin
– Less drive per input capacitance
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Which is Fastest?
• nand32
• nand4-inv-nand4-inv-nand2
• (nand2-inv)4-nand2
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Delay of each
implementation?
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Take Away?
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Lesson
• Large gates are slow / inefficient
– High capacitive load / drive strength
• Small gates can be inefficient
– Need many stages
• Staging over moderate size gates
minimizes delay
• Exact size will be technology dependent
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Admin
• HW5
– Problem 4 – work sizing and delay parts
(a and c) now
– Energy next time
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Ideas
• First order reason in t=R0C0 units
• Gates have different efficiencies
– Drive strength per unit input capacitance
• Without velocity saturation
– Reason to prefer nand over nor
• With velocity saturation (short term),
– nands and nors are similar efficiency
• Large fanin and fanout slow gates
– Decompose into stages
– …but not too much
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