Transcript ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 34: December 3, 2012 Transmission Lines Modeling and TerminationPenn ESE370 Fall2012 -- DeHon.

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 34: December 3, 2012
Transmission Lines
Modeling and Termination
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Penn ESE370 Fall2012 -- DeHon
Transmission Line Agenda
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Where arise?
General wire formulation
Lossless Transmission Line
See in action in lab
Impedance
End of Transmission Line?
Termination
Discuss Lossy
Implications
Penn ESE370 Fall2012 -- DeHon
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From Day 32
• Signal propagate as wave down
transmission line
• V(x,t) = A+Be(x-wt)
– Delay linear in wire length
– Speed
1
c0
w

LC
 r r
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
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Wire “Resistance”
• What is the resistance at Vi ?
• Q to charge Vi?
• Ii given velocity w?
• R = Vi/Ii?
Vi-1
Ii
Vi
Ii+1
Vi+1
Ici
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Wire “Resistance”
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Q=CV
I = dQ/dt
Moving at rate w
I=wCV
R=V/I=1/(wC)

Vi-1
Ii
Vi
Ici
Ii+1
w
1
LC
LC
R
C
Vi+1

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Impedance
• Z0 =R= 1/wC = 1/(C/sqrt(LC))
LC
R
C
L
Z0 
C

Vi-1

Penn ESE370 Fall2012 -- DeHon
Ii
Vi
Ii+1
Vi+1
Ici
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Impedance
• Assuming infinitely long wire,
how look different at Vi, Vi+1, Vi+2 ?
Vi-1
L
Z0 
C
I
Ii
Vi
i+1
Vi+1
Ici
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Impedance
• Transmission line has a characteristic
impedance
– Looks to driving circuit like a resistance
L
Z0 
C
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Infinite Lossless
Transmission Line
• Transmission line looks like
resistive load
L
Z0 
C
Z0

• Input waveform travels down line at
velocity
1
– Without distortion
Penn ESE370 Fall2012 -- DeHon
w
LC
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End of Line
• What happens at the end of the
transmission line?
– Short Circuit
• Hint: what must happen in steady state?
– Terminate with R=Z0
– Open Circuit
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Short
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Terminate R=Z0
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Open
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Longer LC (open)
• 40 Stages
• L=100nH
• C=1pF
1
c0
w

LC
 r r
Stage delay?

• Drive with 2ns Pulse
• No termination (open circuit)
Penn ESE370 Fall2012 -- DeHon
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Pulse Travel RC
• V1,V3,V4,V5,V6 about 10 stages apart
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Analyze End of Line
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Analyze End of Line
• Incident wave Vi=Ii×Z0
• @ T- Vi is voltage on line
• Vt is what goes forward
– Voltage seen by end of line
at T
• Vr is the delta voltage
that starts moving back
towards source at T+
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Penn ESE370 Fall2010 -- DeHon
Analyze End of Line
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Incident wave Vi=Ii×Z0
KCL @ end
KVL @ end
V=IR relationships?
– Which resistances go
with each V?
• Relate all three V’s
using R, Z0
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Penn ESE370 Fall2010 -- DeHon
Analyze End of Line
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Incident wave Vi=Ii×Z0
KCL: Ii=Ir+It
KVL: Vi+Vr=Vt
Vr=Ir×Z0 Ir=Vr/Z0
Vt=It×R
It=Vt/R
Ii=Vi/Z0
V
V r Vt


Z0 Z0 R
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Penn ESE370 Fall2012 -- DeHon
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Analyze End of Line
• Vi+Vr=Vt
Eliminate Vt
Vi V r Vt


Z0 Z0 R
Vi Vr Vi  Vr


Z0 Z0
R
V V V V
i
i
r
r
 

Z0 R Z0 R
Penn ESE370 Fall2012 -- DeHon
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Analyze End of Line
• Vi+Vr=Vt
Vi Vi Vr Vr
 

Z0 R Z0 R
RVi  Z 0Vi  RVr  Z 0Vr

R  Z 0 
Vi 
 Vr
R  Z 0 
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Penn ESE370 Fall2012 -- DeHon
Analyze End of Line
• Vi+Vr=Vt
R  Z 0 
Vi 
 Vr
R  Z 0 
R  Z0 
Vi
1 Vt
R  Z0 

 2R 
Vi 
 Vt
R  Z 0 
Penn ESE370 Fall2012 -- DeHon
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Reflection
• Sanity check with
previous
– Short
– Matched
– Open
R  Z 0 
Vi 
 Vr
R  Z 0 
 2R 
Vi 
 Vt
R  Z 0 
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Pulse Travel RC
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Visualization
• http://www.williamson-labs.com/xmission.htm
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Back to Source
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Back at Source?
• What happens at source?
– Depends on how terminated
– Looks like at sink end
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R≠Z0
• What happens?
– 75 W termination on 50 W line
– “Short-Circuit” source?
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Simulation
• For these, with direct drive from voltage
source
– Source looks like short circuit (not typical of CMOS)
• Source cannot be changed
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50W line, 75W termination
R  Z 0 
75  50
Vr  Vi 
 0.2Vi
 Vi 
75 50
Penn ESE370 Fall2012 -- DeHon R  Z 
0
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Step Response
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Class ended here
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Series Termination
• What happens here?
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Simulation
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Penn ESE370 Fall2012 -- DeHon
Series Termination
• Rseries = Z0
• Initial voltage divider
– Half voltage pulse down line
• End of line open circuit
– sees single transition to full voltage
• Reflection returns to source and sees
termination Rseries = Z0
• No further reflections
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Penn ESE370 Fall2012 -- DeHon
Termination Cases
• Parallel at Sink
– Pix
• Series at Source
– pix
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Penn ESE370 Fall2012 -- DeHon
CMOS Driver / Receiver
• Driver: What does a CMOS driver look
like at the source?
– Id,sat=1200A/m @ 45nm
• Receiver: What does a CMOS
inverter look like at the
sink?
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Penn ESE370 Fall2012 -- DeHon
Idea
• Signal propagate as wave down
transmission line
– Delay linear in wire length
– Speed
– Impedance
1
c0
w

LC
 r r
L
Z0 
C
• Behavior at end of line
depends on termination
• Both src and sink
R  Z 0 
are “ends”
V  V 

r
Penn ESE370 Fall2012 -- DeHon
 R  Z 0 
i
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Admin
• HW7 Thursday
• Last year’s final posted on Fall 2011
syllabus
– No answers now
– Maybe answers at end of week
• Lectures Wednesday and Friday
• Andre out next week before final
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