Transcript ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 10, 2012 Gates from Transistors Penn ESE370 Fall2012 -- DeHon.

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 3: September 10, 2012
Gates from Transistors
1
Penn ESE370 Fall2012 -- DeHon
Previously
• Simplified models for reasoning about
transistor circuits
– Zeroth-order
2
Penn ESE370 Fall2012 -- DeHon
Today
• How to construct static CMOS gates
3
Penn ESE370 Fall2012 -- DeHon
Outline
• Circuit understanding
– Finish zeroth order example
– preclass
• Static CMOS
– Structure
– Inverter
– Construct gate
– Inverting
– Cascading
Penn ESE370 Fall2012 -- DeHon
4
What happens when
Vin=Vdd>Vth
Vgs=0 > Vthp
Vthp=-Vthn
Vgs=-Vdd < Vthp
V2=Gnd
Penn ESE370 Fall2012 -- DeHon
Vgs=Vdd > Vthn
Vgs=0 < Vthn
Vout=Vdd
5
What happens when
Vin=0<Vth
Work on board
Penn ESE370 Fall2012 -- DeHon
6
What happens when
Vin=0<Vth
V2=Vdd
Vout=0
7
Penn ESE370 Fall2012 -- DeHon
What function?
Buffer
• Vin=Vdd  Vout=Vdd
• Vin=0  Vout=0
8
Penn ESE370 Fall2012 -- DeHon
Why Zeroth Order Useful?
• Allows us to reason (mostly) at logic
level about steady-state functionality of
typical gate circuits
• Make sure understand logical function
(achieve logical function) before
worrying about performance details
9
Penn ESE370 Fall2012 -- DeHon
What gate?
10
Penn ESE370 Fall2012 -- DeHon
What function?
11
Penn ESE370 Fall2012 -- DeHon
DeMorgan’s Law
• /f = a + b
• What is f?
12
Penn ESE370 Fall2012 -- DeHon
What function?
13
Penn ESE370 Fall2012 -- DeHon
Static CMOS Gate
14
Penn ESE370 Fall2012 -- DeHon
Static CMOS Gate Structure
15
Penn ESE370 Fall2012 -- DeHon
Static CMOS Gate Structure
16
Penn ESE370 Fall2012 -- DeHon
Static CMOS Gate Structure
• Drives rail-to-rail
(output is Vdd or Gnd)
• Inputs connects to
gates  load is
capacitive
• Once charge
capacitive output,
doesn’t use energy
– (first order)
• Output actively driven
Penn ESE370 Fall2012 -- DeHon
17
Inverter
• Out = /in
18
Penn ESE370 Fall2012 -- DeHon
Inverter
19
Penn ESE370 Fall2012 -- DeHon
Why zeroth-order adequate?
• Static analysis – can ignore capacitors
• Capacitive loads – resistances don’t matter
• Feed forward for gates –
– don’t generally have loops
– can work forward from known values
• Logic drive rail-to-rail
– Don’t have to reason about intermediate voltage
levels
20
Penn ESE370 Fall2012 -- DeHon
What zeroth-order not tell us?
• Delay
• Dynamics
• Behavior if not
– Capacitively loaded
– Acyclic (if there are Loops)
– Rail-to-rail drive
21
Penn ESE370 Fall2012 -- DeHon
Gate Design Example
22
Penn ESE370 Fall2012 -- DeHon
Gate Design
• Design gate to perform: f=(/a+/b)*/c
23
Penn ESE370 Fall2012 -- DeHon
f=(/a+/b)*/c
• Strategy:
1. Use static CMOS
structure
2. Design PMOS
pullup for f
3. Use DeMorgan’s
Law to determine /f
4. Design NMOS
pulldown for /f
24
Penn ESE370 Fall2012 -- DeHon
f=(/a+/b)*/c
• PMOS Pullup for f?
25
Penn ESE370 Fall2012 -- DeHon
f=(/a+/b)*/c
• Use DeMorgan’s
Law to determine /f.
• What is /f ?
26
Penn ESE370 Fall2012 -- DeHon
f=(/a+/b)*/c
• NMOS Pulldown for /f?
27
Penn ESE370 Fall2012 -- DeHon
f=(/a+/b)*/c
a
c
b
28
Penn ESE370 Fall2012 -- DeHon
Static CMOS Source/Drains
• With PMOS on top,
NMOS on bottom
– PMOS source
always at top (near
Vdd)
– NMOS source
always at bottom
(near Gnd)
29
Penn ESE370 Fall2012 -- DeHon
Inverting Gate
30
Penn ESE370 Fall2012 -- DeHon
Inverting Stage
• Each stage of Static CMOS gate is
inverting
31
Penn ESE370 Fall2012 -- DeHon
How do we buffer?
32
Penn ESE370 Fall2012 -- DeHon
How implement OR?
33
Penn ESE370 Fall2012 -- DeHon
Cascading Stages
34
Penn ESE370 Fall2012 -- DeHon
Stages
• Can always cascade “stages” to build
more complex gates
• Could simply build nor2 at circuit level
and assemble arbitrary logic by
combining – universality
– but may not be smallest/fastest/least power
35
Penn ESE370 Fall2012 -- DeHon
Implement: f=a*/b
• Pullup?
• Pulldown?
36
Penn ESE370 Fall2012 -- DeHon
f=a*/b
37
Penn ESE370 Fall2012 -- DeHon
Admin
• Office hours
– Today: Udit 7-8pm Ketterer
– Tuesday: Andre 4-5:30pm Moore/GRS 262
– Wednesday: none (normally Udit 6pm
• Thursday: HW1 due
• design gates will build in lab on Friday
• Friday in Detkin (RCA) Lab
– Please read through HW2, Lab1 details
– Bring USB drive with you to lab on Friday to
store waveforms
38
Penn ESE370 Fall2012 -- DeHon
Big Idea
• Systematic
construction of any
gate from transistors
1. Use static CMOS
structure
2. Design PMOS
pullup for f
3. Use DeMorgan’s
Law to determine /f
4. Design NMOS
pulldown for /f
Penn ESE370 Fall2012 -- DeHon
39