Transcript ppt
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 24, 2011 Ratioed Logic 1 Penn ESE370 Fall2011 -- DeHon Previously • Restoration and Noise Margins • CMOS Gates – Drive rail-to-rail – Only one transistor turned on in steady state • Only subthreshold current in steady state 2 Penn ESE370 Fall2011 -- DeHon Today • Ratioed Gates – Correctness – Performance – Power – Implications 3 Penn ESE370 Fall2011 -- DeHon Note on what about to see • Not clear win • Should be able to analyze – Chance to exercise analysis – Kind of thing you want to be able to analyze • Pattern should recognize • Stepping stone to more interesting things to come… 4 Penn ESE370 Fall2011 -- DeHon Idea • Building both pull-up and pull-down can be expensive – many gates • Seems wasteful to build logic function twice – Once in pullup, once in pulldown – Large capacitance 5 Penn ESE370 Fall2011 -- DeHon Idea • Maybe only need to build one • Build NFET pulldown – Exploit high N mobility • traditional 6 Penn ESE370 Fall2011 -- DeHon Ratioed Inverter • Does this work? – Vout for Vin=0V ? – Vout for Vin=1V ? WP=1 WN= 1 7 Penn ESE370 Fall2011 -- DeHon Ratioed Inverter • Does this work? – Vout for Vin=0V ? – Vout for Vin=1V ? WP=1 WN= 1 8 Penn ESE370 Fall2011 -- DeHon Ratioed Inverter Wn=1 9 Penn ESE370 Fall2011 -- DeHon Ratioed Inverter • How do we need to size N to make it work? WP=1 10 Penn ESE370 Fall2011 -- DeHon DC Transfer Function 11 Penn ESE370 Fall2011 -- DeHon Ratioed Inverter • How do we need to size P to make it work? WN=1 12 Penn ESE370 Fall2011 -- DeHon P vs. N • Conclude: still prefer N to P for ratioed logic – ….at least for now 13 Penn ESE370 Fall2011 -- DeHon Worst-Case Output Drive Strength? • Rdrive? WP=1 14 Penn ESE370 Fall2011 -- DeHon Noise Margin Tradeoff • What is impact of increasing (reducing) noise margin? 15 Penn ESE370 Fall2011 -- DeHon Ratioed Inverter Sizing 16 Penn ESE370 Fall2011 -- DeHon Ratioed Inverter Sizing • What causes knee in curve at high end? 17 Penn ESE370 Fall2011 -- DeHon Size for R0/2 drive? • How do we size for R0/2 drive? 18 Penn ESE370 Fall2011 -- DeHon Compare Static CMOS For Rdrive=R0/2 inverter • Total Transistor Width? • Input capacitance load? 19 Penn ESE370 Fall2011 -- DeHon Power? • Istatic ? • Output high? – Ileak • Output low? – Ipmos_on – Vdd/(R0/2) -- for our sample case 20 Penn ESE370 Fall2011 -- DeHon Power • Ptot ≈ a(½Cload+Csc)V2f +PlowV2/Rpon +(1-Plow)VI’s(W/L)e-Vt/(nkT/q) 21 Penn ESE370 Fall2011 -- DeHon How size for R0/2 drive? 22 Penn ESE370 Fall2011 -- DeHon How size for R0/2 drive? 23 Penn ESE370 Fall2011 -- DeHon Which Implementation is faster in ratioed logic? 24 Penn ESE370 Fall2011 -- DeHon Illustrates • Preferred gate changes 25 Penn ESE370 Fall2011 -- DeHon How size for R0/2 drive? • How size K-input nor? 26 Penn ESE370 Fall2011 -- DeHon When better than CMOS nor-k? • Better = smaller, lower input capacitance 27 Penn ESE370 Fall2011 -- DeHon Energy vs. Power? • Which do we care about? – Battery operated devices? – Desktops? – Pay for energy by kW-Hr? 28 Penn ESE370 Fall2011 -- DeHon Admin • Project – Should have read it – Built and simulated baseline? • Do it by Wednesday – Started list of optimizations to try? • If don’t have list by Wed, talk with Paul… 29 Penn ESE370 Fall2011 -- DeHon Ideas • There are other logic disciplines • We have the tools to analyze • Ratioed Logic – Tradeoff noise margin for • Reduced area? Capacitive load? – Dissipates static power in one mode 30 Penn ESE370 Fall2011 -- DeHon