Transcript slides

Transition Delay Fault
Testing of Microprocessors
by Spectral Method
Nitin Yogi and Vishwani D. Agrawal
Auburn University
Department of ECE
Auburn, AL 36849, USA
March 6, 2007
39th Southeastern Symposium on System Theory
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Outline

Introduction



Problem and Approach




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Defects and transition delay fault model
Microprocessor testing Issues
Register-transfer level modeling of transition delay faults
Spectral analysis and test generation
Design for Testability
Experimental Results
Conclusion
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39th Southeastern Symposium on System Theory
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An Open Circuit Defect
Reference: W. Maly, “Realistic Fault Modeling for VLSI Testing”, Proceedings of the 24th ACM/IEEE Design
Automation Conference, 1987, Miami Beach, Florida, Pages 173-180.
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A Bridging Defect
Reference: W. Maly, “Realistic Fault Modeling for VLSI Testing”, Proceedings of the 24th ACM/IEEE Design
Automation Conference, 1987, Miami Beach, Florida, Pages 173-180.
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A Possible Delay Defect
Reference: W. Maly, “Realistic Fault Modeling for VLSI Testing”, Proceedings of the 24th ACM/IEEE Design
Automation Conference, 1987, Miami Beach, Florida, Pages 173-180.
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Stuck-at Fault Model
Fault activated
Stuck-at 0
A
Fault detected
B
Y
C
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Transition (Delay) Fault Model
Fault activated
Slow-to-rise
fault
A
Fault detected
B
Y
C
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Microprocessor Testing Issues
Issues arising from Increased Design Complexity
 Increased Demands on Testing
 A Viable Test Method: Functional at-speed tests
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Need Fault-Oriented Test Generation Methods
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Advantages: easy to derive; cover many defects
Disadvantages: Long test sequences; full coverage not
guaranteed
Test pattern generators work at gate level
Have very high complexity
RTL Test Generation

Advantages:


Low testing complexity
Early detection of testability issues
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Problem and Approach

The problem is …


Develop an RTL ATPG method to generate
functional at-speed tests.
And our approach is …

Circuit characterization using RTL:
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
RTL test generation
Analysis of information content and noise in RTL
vectors.
Test generation for gate-level implementation:
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
Generation of spectral vectors
Fault simulation and vector compaction
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Faults Modeled at Register-Transfer Level
Inputs
Combinational
Logic
Outputs
RTL modules
RTL
transition
delay fault
sites
FF
FF
A circuit is an interconnect of several RTL modules.
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.
.
.
Input 2
Input 1
Analyzing Bit-Streams of RTL Tests
Vector 1
Vector 2
.
.
.
Bit-stream
0 to -1
Bit-stream of
Input 2
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Spectral Characterization of a Bit-Stream
Bit stream
to analyze
Correlating with Walsh functions by
multiplying with Hadamard matrix.
Hadamard Matrix H(3)
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Bit
stream
Spectral
coeffs.
Essential component
(others regarded noise)
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Generation of New Bit-Streams
Perturbation
Spectral
components
Generation of new bit-stream by
multiplying with Hadamard matrix
Essential
component
retained; noise
components
randomly
perturbed
Sign function
New bit stream
-1 to 0
Bits changed
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PARWAN Processor
Reference: Z. Navabi, Analysis and Modeling of Digital Systems. New York: McGraw-Hill, 1993.
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Power Spectrum for “Interrupt” Bit-Stream
Analysis of 128 test vectors.
Normalized Power
Essential
components
Some noise
components
Random
level
(1/128)
Spectral Coefficients
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Power Spectrum for “DataIn[5]” Signal
Normalized Power
Analysis of 128 test vectors.
Some
essential
components
Some noise
components
Theoretical
random noise
level
(1/128)
Spectral Coefficients
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RTL Design for Testability (DFT)

Goals of DFT:

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Improve fault coverage
Most hard-to-detect transition faults were
experimentally found to have poor observability
XOR tree as DFT
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Low area overhead
Low performance penalty
Hard-to-detect RTL faults used for observation test points
24 observation test points selected
XOR tree
Hard-to-detect
RTL transition
faults
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To test
output
17
Experimental Results
RTL transition fault characterization
PARWAN processor
No of RTL
Transition
Faults
No. of
vectors
737
160
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CPU (s)
RTL coverage
(%)
Gate-level
fault
coverage(%)
3652
77.07%
47.84%
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Experimental Results
ATPG used
RTL-spectral for
transition faults
RTL-spectral
combined stuck-at &
transition tests
Gate-level FlexTest
for transition faults
Random vectors
Version of
PARWAN
circuit
CPU
secs.*
No. of
vectors
Stuck-at
fault cov.
(%)
Transition
fault cov.
(%)
Original
6428
6700
97.60
81.85
DFT for t-f
6428
5120
98.25
85.94
Original
9027
98.47
81.85
DFT for s-a-f **
7086
98.91
85.87
DFT for t-f
7086
98.77
86.27
Original
43574
1318
92.44
73.79
DFT for t-f
40119
1444
96.29
81.90
Original
51200
82.28
58.67
DFT for s-a-f **
51200
86.20
65.82
* Sun Ultra 5, 256MB RAM
** N. Yogi and V. D. Agrawal, “Spectral RTL Test Generation for Microprocessors,” in Proc. 20th
International Conf. VLSI Design, Jan. 2007, pp. 473-478.
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Experimental Results
PARWAN without DFT
Test Coverage (%)
100
80
Stuck-at
Fault
Coverage
60
Transition
Fault
Coverage
40
20
Transition
Vectors
Stuck-at Vectors
0
1
10
100
1000
10000
No. of vectors
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Experimental Results
PARWAN with DFT
Test Coverage (%)
100
80
Stuck-at
Fault
Coverage
60
Transition
Fault
Coverage
40
20
Transition
Vectors
Stuck-at Vectors
0
1
10
100
1000
10000
No. of vectors
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Conclusion
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
Spectral RTL ATPG technique applied to PARWAN
processor for transition delay faults.
Proposed ATPG method provides:
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Good quality “almost” functional at-speed transition delay tests
Lower test generation complexity
Enables testability appraisal at RTL
RTL based XOR tree as DFT improved fault
coverage.
Test optimization for multiple fault models:

Yogi and Agrawal, “Optimizing Tests for Multiple Fault Models,”
submitted to the North Atlantic Test Workshop 2007.
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Thank You !
Questions ?
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