Transcript slides

Logic Redesign for
Low Power
ELEC 6970 Project Presentation
By Nitin Yogi
Nov. 29, 2005
ELEC6970-001 Class Presentation
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Outline
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Low Power Logic Synthesis
Low Power Optimization Techniques
Redundancy Insertion
Logic Transformation
Multiplier Cell Optimization
Experimental Results
Summary and Conclusion
What I learnt !
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Low Power Logic Synthesis
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Sources of Power
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Dynamic power
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Signal transitions
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Method : Area optimized logic synthesis
Power α Transistor Leakage and Short-circuit current
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Leakage
Power α Area
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Short-circuit
Static
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Logic activity
Glitches
Method : Optimized transistor level design for gates
Power α Signal Activity of Circuit
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Method : Low Power Logic Synthesis
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Low Power Optimization techniques
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Technology Independent Optimization
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Algebraic Logic Restructuring
Kernel and Cube Extraction
 Iterative extraction and re-substitution of subexpressions
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Post Mapping Structural Optimization
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Redundancy Insertion
Logic Transformations
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Post-mapping Structural Optimization
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Redundancy Insertion
Redundancy is inserted into the circuit to minimize a
cost function.
3 elements required in the process
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Suitable circuit location for redundancy insertion
Candidate type of redundancy
Cost function
3 steps involved
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Identifying candidates for redundancy insertion at a suitable
circuit location for minimum cost function.
Applying logic transformation to insert redundancy
Reducing the circuit by removing other generated
redundancies by logic transformation.
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Post-mapping Structural Optimization
Finding Circuit Locations for Redundancy Insertion
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Identify Source and Target locations using don’t care implications
Possible target location
x
x
A
x
x
B x
0
Y
0
C
Source location
D
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Post-mapping Structural Optimization
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Candidate Redundancy insertions
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Redundancy insertions to input of gates
x
x
0
1
‘0’ implication don’t care
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‘1’ implication don’t care
Used to reduce signal activity at the output of a
gate using another signal.
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Post-mapping Structural Optimization
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Gate Insertion:
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Post-mapping Structural Optimization
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Circuit Reduction to eliminate unwanted
redundancies
Redundancy identification methods:
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ATPG based
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Use of exhaustive ATPG to find redundant faults
Redundant faults signify redundant logic
Fault independent
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Controllability and Observability analysis
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Post-mapping Structural Optimization
Logic Transformations
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Permissible function:
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Gate Substitution
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If all the network primary output
functions do not change after the
function realized at a signal line Li
is replaced by a function f , then the
function f is called a permissible
function for the signal line Li .
Replace a target signal line with the
candidate signal line having the
same function.
Inverter Insertion
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Replace a target signal line with the
inverted candidate signal line
having the same function.
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Post-mapping Structural Optimization
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Logic Transformations
Eliminate inverters on signals with high activity
Discourage the implementation of EX-OR gates
EX-OR gate example:
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Y = A•B + A•B
= (A•B) + (A•B)
= (A + B) + A•B
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Multiplier Cell
B3
0
B2
0
B1
0
B0
0
B
Sum input
A0
0
A
Y0
0
A1
Y1
Carry out
A2
0
Full
adder
Carry in
Y2
A3
0
Y7
Y6
Y5
Y4
Sum output
Y3
Cell
Array
Full Adder
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Multiplier Cell
EX-OR
EX-OR
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Multiplier Cell
Modified
EX-OR
EX-OR
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Multiplier Cell
Modified - 2
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Multiplier Cell
Leonardo (delay optimized)
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Multiplier Cell
Leonardo (area optimized)
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Experimental Results
Multiplier Cell
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Design and simulation details
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Design Entry tool: Design Architect
Simulation tool : Eldo
(timing and power analysis)
Technology library: tsmc 0.18um (VDD = 1.8V)
Input Vectors:
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Inputs: frequencies in multiples of 2
Output transitions generated:
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Sum Out (Sout) : 25
Carry Out (Cout) : 12
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Multiplier Cell Results
Unopt.
Opt.
Leo_Area
Leo_Delay
Static Power
367.04 pW 201.93 pW 168.94 pW 194.28 pW
Dyn. Power
27.08 uW
17.39 uW
20.83 uW
21.28 uW
Avg.
276.13 ps
287.77 ps
225.85 ps
189.16 ps
Peak
328.45 ps
345.74 ps
257.23 ps
255.17 ps
Avg.
226.08 ps
173.77 ps
80.59 ps
90.16 ps
Peak
237.07 ps
177.02 ps
108.62 ps
96.60 ps
Tdelay
(A/B=>Sout)
Tdelay
(A/B=>Cout)
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Summary and Conclusion
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Post Mapped Structural Optimization techniques for Low
Power prove to be effective.
Percentage reduction in power consumption of optimized
Multiplier Cell as compared to:
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Percentage increase in critical path delay of optimized
Multiplier Cell as compared to:
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Unoptimized cell: ~35.7%
Leonardo generated: ~15%
Unoptimized cell: ~35.7%
Leonardo generated: ~50%
Effective cost functions to include delay constraints will
enhance the quality of the circuits.
Effective algorithms for structural optimization.
32 x 32 bit Multiplier power optimization.
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What I learnt !
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Low Power Logic Synthesis
 Logic synthesis
 Logic optimization
 Redundancy insertion, identification and
elimination
Use of EDA tools for timing and power analysis
Start your projects early! (wish I would have)
Large patience required with EDA tools!
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References
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S. Devadas, S. Malik, “A Survey of Optimization Techniques Targeting Low Power
VLSI Circuits,” Annual ACM IEEE Design Automation Conference, Proceedings of
the 32nd ACM/IEEE conference on Design automation, San Francisco, California,
United States, pp. 242 – 247, 1995
Pradhan D.K., Chatterjee M., Swarna M.V., Kunz W, “Gate-level synthesis for lowpower using new transformations,” Low Power Electronics and Design, 1996,
International Symposium on, pp 297-300, Aug 1996
Wang Q., Vrudhula S.B.K., “Multi-level logic optimization for low power using
local logic transformations,” Computer-Aided Design, 1996. ICCAD-96., 1996
IEEE/ACM International Conference on
10-14 Nov. 1996 Page(s):270 – 277
Shih-Chieh Chang, Marek-Sadowska M, “Perturb And Simplify: Multi-level
Boolean Network Optimizer,” Computer-Aided Design, 1994., IEEE/ACM
International Conference on November 6-10, 1994 Page(s):2 - 5
R. V. Menon, S. Chennupati, N. K. Samala, D. Radhakrishnan and B. Izadi, “Power
Optimized Combinational Logic Design,” Proceedings of the International
Conference on Embedded Systems and Applications, pp. 223 - 227, June 2003.
W. Kunz, “Multi-level Logic Optimization By Implication Analysis,” ComputerAided Design, 1994., IEEE/ACM International Conference on November 6-10,
1994 Page(s):6 - 13
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References
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Roy K., Prasad S.C., “Circuit activity based logic synthesis for low power
reliable operations,” Very Large Scale Integration (VLSI) Systems, IEEE
Transactions on
Volume 1, Issue 4, Dec. 1993, pp 503 – 513
Ki-Wook Kim, Ting Ting Hwang, Liu C.L., Sung-Mo Kang, “Logic
transformation for low power synthesis,” Design, Automation and Test in
Europe Conference and Exhibition 1999. Proceedings, pp158 – 162, March 1999
Brzozowski I., Kos A., “Minimisation of power consumption in digital
integrated circuits by reduction of switching activity,” EUROMICRO
Conference, 1999. Proceedings. 25th Volume 1, 8-10 Sept. 1999 Page(s):376 - 380
vol.1 M. A. Iyer and M. Abramovici, “Low-Cost Redundancy Identification for
Combinational Circuits,” in Proc. 7th International Conf. on VLSI design, pp. 315317, January 1994.
V.D. Agrawal; M.L. Bushnell, Qing Lin, “Redundancy identification using
transitive closure,” Test Symposium, 1996., Proceedings of the Fifth Asian 20-22
Nov. 1996 Page(s):4 – 9
Abramovici M., Iyer M.A., “One-Pass Redundancy Identification and Removal,”
Test Conference, 1992. Proceedings., International
Sept. 20-24 1992 Page(s):807
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Thank You!
Questions ???
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