Transcript slides

Reducing Voltage Supply
Jins Davis Alexander
1
Nov. 29, 2005
ELEC6970-001 Class
Presentation
Objective…
2

To reduce the power consumption by
reducing VDD supply voltage and seeing its
effect on power, delay and area.

No effect on area.
Nov. 29, 2005
ELEC6970-001 Class
Presentation
What We Know….
3

Power Consumption is a quadratic function
of Voltage.

Decrease in supply Voltage increases the
overall delay.
Nov. 29, 2005
ELEC6970-001 Class
Presentation
Power and Delay
4

Power =

Delay=
CVDD2
KVDD
───────
(VDD – Vt)α
(from alpha-power model)
Nov. 29, 2005
ELEC6970-001 Class
Presentation
What I have done…
5

Designed N*N array multiplier using VHDL.

Used ELDO for power analysis and
calculation of delay.

First simulated basic cell and found delay of
Sumout to be greater than Cout.
Nov. 29, 2005
ELEC6970-001 Class
Presentation
6

Forced pulse signals for all possible vectors
at inputs A and B for a 4x4 multiplier.

Compared signal A[0] with Sum[2N-2] to
calculate the overall worst case delay.
Nov. 29, 2005
ELEC6970-001 Class
Presentation
Results of 4x4 array multiplier.
7
Voltage
Avg.Power (uW) Delay (ns)
1.8
106.32
1.76
1.5
66.43
1.934
1.2
36.49
2.34
1
21.71
3.99
Nov. 29, 2005
ELEC6970-001 Class
Presentation
% Results
8
Voltage(%
Decrease)
Avg Power(%
Decrease)
Delay (%
Increase)
16.7%
37.5%
10%
33.3%
65.6%
33%
44.4%
79.5%
127%
Nov. 29, 2005
ELEC6970-001 Class
Presentation
Dynamic Power vs. Voltage
9
Nov. 29, 2005
ELEC6970-001 Class
Presentation
Delay vs. Voltage
10
Nov. 29, 2005
ELEC6970-001 Class
Presentation
Static Power vs. Voltage
11
Nov. 29, 2005
ELEC6970-001 Class
Presentation
Conclusion.



12
Reducing Voltage decrease power
significantly.
However at lower voltages the delay
increase is very significant.
Transistor sizing, parallel processing can
help reduce the overall delay.
Nov. 29, 2005
ELEC6970-001 Class
Presentation
THANK YOU.
13
Nov. 29, 2005
ELEC6970-001 Class
Presentation