Transcript talk
Nelson Sunwoo
Modify s5378 to full scan design
Modify scan flip flops to prevent switching in
combination logic
Compare average power consumption of
original and enhanced design
Scan shift causes redundant switching in
combination logic.
Power dissipation during the test mode is up
to three times higher than normal mode.
Primary
inputs
Primary
outputs
Combinational
logic
D
SI
Scan
Q
flipflops
Scan
flipflops
...
Scan
flipflops
SO
D
SI
0
mux
Scan Flip Flop
SO
DFF
Q
1
SE
SE
Scan flip-flop
technology: TSMC 0.18um
Vdd: 1.8V
clock speed: 1GHz
1000 random vector sets
- inputs (0.5 activity)
- Scan in (random)
Average Power
Original design
Modified design
Power reduction
52.559mW
36.252mW
31 %
S. Gerstendrfer and H. J. Wunderlich, Minimized Power Consumption for Scan-based BIST,
International Test Conference, 1999, pp 77-84.