Transcript xft_2b_plans.ppt

XFT2B: Plans and Tasks
Richard E. Hughes
XFT Workshop FNAL
19 December 2003; p.1
Types of Tasks
 Software
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Functional simulation (in C++)
FPGA firmware
Mapping software – turns databases into firmware
Teststand software
 Building “stuff”
 Design and layout of prototypes
 Boards will be produced and stuffed externally
 Testing
 Can be done anywhere there is experience
 Will require good coordination if done by many groups
 Commissioning
 Done at FNAL
 Requires experts at teststand software
Richard E. Hughes
XFT Workshop FNAL
19 December 2003; p.2
Overview of Simulation Tasks
 Simulation studies that need to be done:
 With both current design and upgraded design
 What happens as a function of luminosity
 Trigger rates
 Resolution in pt and phi
 Similar question for COT hit efficiency effects
 What is the impact of each possible upgrade
 Finders+Linkers+Stereo
 Improved timing in finders
 Improved slope info used in Linkers
 Stereo only
 Finders only with improved timing
 Modification of upgrade simulation
 Have version for upgraded Linker+Finder (Needs to be validated)
 No version for Stereo, but addition should be straightforward
Richard E. Hughes
XFT Workshop FNAL
19 December 2003; p.3
Simulation Tools
 Have two versions of the simulation
 Full AC++ versions
 Produces XFFD, XFLD banks
 Runs in TrigMon and used in monitoring
 “ROOT” version
 Same code as AC++ version
 Run off of TopNtuple (which also has tracking info: hits, tracks, etc)
 Can use COTD bank as input or Mezzanine card data as input
 Output is convenient for ROOT analysis
 Most convenient is ROOT version
 Can easily change number of misses, road files, etc
 Can modify XFT simulation to see impact of proposed changes
 Adding stereo here should be straightforward
Richard E. Hughes
XFT Workshop FNAL
19 December 2003; p.4
Other Simulation Tasks
 Will leading edge info help?
 Can this be done with 6 time bins defined like present system?
 Or does new TDC need to identify these?
 Do we want even finer (better than 6) time bins?
 This impacts data transfer from XTC to Finders
 Limit is 22nsec safely, and this limits us to 6 time bins
Richard E. Hughes
XFT Workshop FNAL
19 December 2003; p.5
FPGA
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FPGA Firmware development
 Implementing new design in FPGA
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Altera VS Xilinx vs ???
Does it fit?
Is it fast enough?
How difficult (hand layout)
How expensive?
 Testing in actual chip.
 Previous experience was that chip simulation matched real chip
behavior well
 Is this true for new devices/simulations
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We have a baseline for both upgraded Finder and Linker
algorithms
 Have started on Linker and Finder implementation
Richard E. Hughes
XFT Workshop FNAL
19 December 2003; p.6
Test Stands
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Test Stand:
 Setup of Test Stand
 Can bring up stands we used for current device
 We found this was somewhat challenging.
 We need a test stand at FNAL
 More test stands at other institutions would be fine
 “Building” boards at one institution, the testing other places would
definitely work
 Software
 Basic talking to board
 Use current version
 Specific tests for checkout
 Dependent on setup of final boards
Richard E. Hughes
XFT Workshop FNAL
19 December 2003; p.7
Other Stuff
 Stereo System
 Simulation works needs to be complete before anything else!
 Tester boards
 Feeding/capturing data to/from new finder?
 Feeding/capturing data to/from new linker?
Richard E. Hughes
XFT Workshop FNAL
19 December 2003; p.8