Transcript Applied Logic & Computation in System Design - An invitation to A L

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Applied Logic & Computation in System Design
- An invitation to ALCom Lab
Jie-Hong R. Jiang
江介宏
DEE/GIEE
National Taiwan University
10/13/2006
About ALCom Lab
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Founded in August 2005
Caring about solving a good problem
cleverly
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We are cooking a pleasant research
environment and a culture of creativity
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Regular boardgame nights
Puzzle solving
Focus/study groups
…
Aiming high and identifying a niche
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New blood wanted!
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We desperately eager for talented students
joining us to claim challenging and exciting
research projects
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Yes, you are one of the talents!
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Where are we heading?
Verification
Optimization
Foundations
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Challenges
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Verification
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Optimization
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60-80% design time is spent on verification
3-to-1 head count ratio between verification
engineers and logic designers
Stringent design constraints on
power/timing/yield, etc.
Foundations
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Design beyond silicon? New models of
computation?
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Equivalence verification
Algorithm
Architecture 1
(e.g. synchronous)
?
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Architecture 2
(e.g. asynchronous)
=
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register-transfer level
=
?
?
gate level 1 = gate level 2
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Property verification
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Identify invariants
Ex.
+
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1 + 2 +…+n
n + n-1 + … + 1
Apply induction
Ex.
x
y
?
?
z = xy
x
y
?
x-1
y
?
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+
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Synthesis & optimization
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Existing IP
O
X
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More info
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Contact me at
[email protected]
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Consult webpage at
http://alcom.ee.ntu.edu.tw
http://cc.ee.ntu.edu.tw/~jhjiang
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