Transcript Device Interface Board for Wireless LAN Testing Team
Faculty Advisor
Dr. Weber
Team Members
Matthew Dahms – EE Justine Skibbe – EE Joseph Chongo – EE
Device Interface Board for Wireless LAN Testing
Team
May 06-15
Client
ECpE Department
February 9, 2006
Presentation Outline
Project Overview Introduction Problem Statement Operating Environment Intended Users & Uses Assumptions and Limitations End-Product Description Project Activities Previous Accomplishments Technology Considerations Present Accomplishments Planned Activities Resources & Schedule Estimated Resources Schedules Closure Materials Additional Work Lessons Learned Risk & Management Closing Summary Figure 1: Teradyne Lab Entrance
Definitions
ASK modulation – Amplitude shift keying. In this modulation scheme the amplitude is varied to indicate logic 0’s and 1’s DUT – Device under test (positive edge D flip-flop) FPGA – Field programmable gate array. Used to test the DUT after receiving signals from the Teradyne tester Header – Preamble bits sent prior to the sending of information in a data packet voltage 1 0 1 0 D3 D2 D1 D0 Header Data Packet Figure 2: Data Packet and Header time
Definitions (cont.)
NRZ – Non-return to zero. Using NRZ, a logic 1 bit is sent as a high value and a logic 0 bit is sent as a low value. PLL – Phase-locked loop RZ – Return to zero. This is the opposite of NRZ data. The signal state is determined by the voltage during the first half of each data binary digit. The signal returns to a resting state (called zero) during the second half of each bit.
Teradyne Integra J750 integrated circuits. – Tester donated to Iowa State University by Teradyne. It is used in the testing of printed circuit boards and
Project Overview
Acknowledgement
Dr. Weber Nathaniel Gibbs Jason Boyd
Project Overview
Problem Statement In Fall 2004, ISU’s ECE Department introduced a senior design project with the goal of developing a wireless interface capable of receiving test signals and transmitting results to the department’s Teradyne Integra J750 tester. For this project, the goal is to modify the current setup so that the wireless interface shall be capable of recovering a clock signal transmitted by the Teradyne system.
Figure 3: Teradyne Integra J750
Project Overview
Assumptions A sufficient clock-training signal can be sent by the Teradyne J750 over the S/R network to initialize the clock recovering circuitry. The clock recovering circuitry will be able to interact with the existing FPGA. The current wireless communication network can transmit up to five feet.
This assumption is based on the May05 team’s documentation. The phase difference between the system clock of the Teradyne J750 and the recovered clock at the wireless interface will not be greater than the overall system clock frequency.
Project Overview
Limitations The Teradyne J750 is sensitive to temperature fluctuations and must operate within the calibrated temperature.
To avoid the loss of data, the maximum rate at which user can send data is at 115.2 Kbps. The existing transmitter and receiver communicate at 916.5 MHz. Therefore, nearby wireless signals at similar frequencies may disrupt the setup. The communication link shall be limited to one frequency. Limited to using only one FPGA. Using two additional FPGA’s, it would be possible to encode/decode the clock and test data into a single data stream. Figure 4: Temperature Requirements
Project Overview
Intended Users The user has knowledge in electrical and/or computer engineering.
The user has previous experience testing circuits with the Teradyne J750.
Intended Uses Functional test of a digital device (Future) Wireless chipset test
Project Overview
End-Product and Other Deliverables Wireless interface with clock recovery circuit Demonstration of wireless test Update the manual for wireless test operation Figure 5: Cover page of wireless manual
Project Activities
Previous Accomplishments
May 05-29 Accomplishments Parallel-Serial Conversion Transmitters and Receivers Processing Device
Previous Accomplishments
Parallel-Serial Conversion Needed to convert parallel test data into serial test data Chose to use a shift register Figure 6: Shift Register attached to daughterboard
Previous Accomplishments
Transmitters and Receivers TRM1 RCV1 TRM2 Figure 7: Tx/Rx PCBs RCV2
Previous Accomplishments
FPGA Used to recognize header signal Identifies test data Presents test data to DUT Presents reply to S/R network Figure 8: FPGA
Figure 9: Final System Setup
Project Activities
Project Definition Part of the May 05 team’s project definition was to include a clock recovery circuit, but due to timing constraints was unable to do so.
May 06 goal is to integrate a PLL for clock recovery with the existing network.
Project Activities
System Block Diagram
Figure 10: Proposed final setup block diagram
Project Activities
Technology Considerations Manchester vs. PLL NRZ to RZ Conversion
Technology Considerations
Manchester Encoding Original Signal Logic 0 Logic 1 Value Sent 0 to 1 (upward transition at bit centre) 1 to 0 (downward transition at bit centre)
The waveform for a Manchester encoded bit stream carrying the sequence of bits 110100
Figure 11: Graphical representation of Manchester encoding
Technology Considerations
Manchester Encoding Very easy to implement Clock phase and frequency are both present Too fast for current transmitters and receivers!
Technology Considerations
Phase Locked Loop Must be “trained” Test data must follow a training signal More difficult to implement Don’t have to build new transmitters and receivers
Project Activities
Figure 12: Internal Components of a PLL
Project Activities
Phase Detector Type I – XOR *Type II – Generates lead or lag pulses Voltage Controlled Oscillator (VCO) Centered at 115.2 KHz Frequencies too far off of center frequency will not lock
Project Activities
Figure 13: Internal PLL Schematic
Project Activities
Monostable Multivibrators Chosen to convert NRZ data to RZ data Must use an external RC combination to specify pulse widths
Project Activities
Figure 14: NRZ to RZ converter circuit with I/O waveforms
Project Activities
Software FPGA serves as “brains” of system Verilog chosen by previous team to program FPGA New prototype code complete
Project Activities
Present Accomplishments Hardware Selected Previous team’s project setup and tested PLL Monostable Multivibrators Software Prototype control software for FPGA written IG-XL test template written
Project Activities
Planned Design/Test Activities Build and test NRZ to RZ converter Build and test PLL circuitry Put new circuitry on printed circuit board Modify FPGA code as necessary Test functional range of wireless interface
Resources & Schedule
Schedule
Expected Original Actual
Schedule (cont.)
Expected Original Actual
Personal Effort
Personal Time Committment
Problem Definition Tech Selection End Product Design End Product Prototype End Product Testing Personnel
Matt Dahms Joe Chongo Srisarath Patneedi Justine Skibbe Total 9* 10* 13* 10* 42* 15* 26* 10* 11* 62* 45 60 55* 50 210 72 59 ** 74 205 64 61 ** 63 188 *Completed hours ** Left on Co-op
End Product Document End Product Demo
35 42 ** 32 109 15 10 ** 16 41
Project reporting Est. Total
16 26 ** 11 53 271 294 78** 267 910
Previous Team Resources
Financial Resources (w/o labor)
Item
Printing of project poster Teradyne Integra J750 Test System PLL Chip Dual Monostable Multivibrator Supplementary (Res, Cap, etc.)
Total Team hours
12hrs 0hrs 0hrs 0hrs 0hrs
0hrs Other Hours
0hrs 0hrs 0hrs 0hrs 0hrs
0hrs Cost
Donated Donated
$1.93
$0.53
$10.00
$12.46
Financial Resources (w/ labor)
Item W/O Labor With Labor Parts and Materials:
a. Printing of project poster b. Teradyne Integra J750 Test System c. Clock Recovery Chip d. Dual Monostable Multivib e. Supplementary (Res, Cap, etc.)
Labor at $12.00 per hour:
a. Matthew Dahms b. Joseph Chongo c. Srisarath Patneedi d. Justine Skibbe
Donated Donated
$1.93
$0.53
$10.00
Donated Donated
$1.93
$0.53
$10.00
$2,880 $3,024 $2,868 $2,928 Subtotal
Total
$11,700
$11,712.46
$12.46
Closure Materials
Risk Management
Risk: Losing Team Member Management: All members keep detailed & organized notes Risk: Loss of Data Management: All data will be backed up using team gmail account Risk: Parts Malfunction Management: Meticulous care in ESD procedures (using ESD bands)
Closing Materials
Lessons Learned What technical knowledge was gained?
FPGA implementation Teradyne Integra J750 usage Clock recovery methods System integration
Closing Materials
Lessons Learned What went well?
May05 System still works!
Teamwork Learned to work in arctic environments (19 degrees C inside Teradyne lab) What did not go well?
Locating May05 equipment Initial Teradyne J750 setup and test Uploading program to FPGA FPGA input pins
Closing Materials
Closing Summary Problem – Integrate clock recovery circuitry into current system Solution Use PLL for clock recovery Modify FPGA program to incorporate new components