David Hover Jonathan Tate Robert Benson Paul Niewoonder

Primary Goal  Embedded Software Graphics Accelerator  Shader Unit    Media-Centric Co-Processor High Floating-Point Computation Performance Graphical Computation  Complete Software Graphics Pipeline

Demonstration Hardware  FPGA Board  Outputs   Monitor LEDs  Inputs    Programming Inputs (JTAG) Buttons Knobs

Demonstration Software  Main User Interface  Benchmarks  Demos  Game  Tetrisphere Clone

Approach

Implementation  Hardware  Cyclone III FPGAs  DDR SDRAM (512MBit)  Tricolor LEDs  Serial Programming Device (EPCS)  DAC  8 Directional Joystick

Implementation (cont.)  Communication Methods  DDR For FPGA/Memory  LVDS For FPGA/FPGA  Software  Assembler  OpenGL Like

Implementation (cont.)  Logic  Prebuilt    SOPC Builder Memory Controllers NIOS  Custom    Caches LVDS to AVALON Bridge Shader

Preliminary Cost Estimate Expenses Lobster Leg FPGA Abdomen FPGA Memory Discrete/Power I/O Board Total Both Revisions Crab Leg FPGA Abdomen FPGA Memory Discrete/Power I/O Board Total $ 60 $ 30 $ 6 $ 100 $ 50 $ 70 $ 60 $ 30 $ 6 $ 150 $ 50 $ 200 Total Costs Unit Cost Quantity Extended 2 1 2 1 1 1 6 1 6 1 1 1 $ 120 $ 30 $ 12 $ 100 $ 50 $ 70 $ 382 $ 360 $ 30 $ 36 $ 100 $ 50 $ 70 646 $ 764 $ 646 $1,410 Funding Sources UROP Northrop Grumman Group Members Total $ 500 $ 200 $ 800 $1,500

Schedule

Division of Labor  Jonathan Tate  Lead Designer  Logic Design  Graphics Pipeline  David Hover  Assembler  User Application Software  Robert Benson  Administrator  Board Design  User Application Software  Paul Niewoonder  Logic Design  Case  Graphics Pipeline

Risks and Contingencies  Medium Risk  Lobster Requires >2 Revisions   Parallel Design The Larger Boards Remove Them From Design  Low Risk    Lobster Requires >4 Revisions  FPGA Development Board Critical Design Flaw – Leg  Quick Redesign – Fit Single FPGA Critical Design Flaw – Shader  Quick Redesign - Software Use NIOS Only

Risks and Contingencies (cont.)  Low Risk (cont.)  Damaged Board Night Before   FPGA Development Board Pre-Prepped Backup  Funds Shortage     Project Designed Around Budget Donations or Student Discounts Remove Functionality/Parts Additional Contributions From Team

Risks and Contingencies (cont.)  Low Risk (cont.)  Shipping Errors  Order Early  Parts Availability   Order Early Redesign If Necessary  Team Member Unavailability  Schedule Allows Short Absence

QUESTIONS?