Transcript 8xADC AMC board Tomasz Klonowski Warsaw University of Technology

8xADC AMC board
Tomasz Klonowski
[email protected]
Warsaw University of Technology
PERG – ISE
3.12.2007
Requirements
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8xADC (100 MHz) + FPGA for data acquisition and processing
Form factor: AMC.1 (with PCIExpress), single width
ADC: 14-16 bit, ~100 MHz sample rate, conversion time 7 maximum
clocks
FPGA: Virtex 5 with external memory (2-4 MB, 250 MHz)
2 EEPROMs for FPGA
2 different clocks (configurable) for ADC 1-4 and ADC 5-8
clock distribution stability better than 5 ps
IPMI
additional signals from rear
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8x analog signal 50-100 MHz through signal conditioning connected to ADC
6x clock up to 100 MHz, LVDS bus, jitter less than 5 ps
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2 of them connected to FPGA and ADC (user can choose clock for ADCs)
4 clocks connected to FPGA, LVDS bus
Block Diagram
AMC connector A+
Analog
signals
1-8
Clocks 1-2
ADC
5-8
AD6645
AD6645
Data
8x16
bits
PCI
Express
JTAG
I2C
uC
Interconnector
Atmega 128
Data
8 bits
Clock
distribution
Data
enable
Clocks 3-6
EEPROM
XCF16P
Clock
configuration
bus
FPGA
Virtex5
XC5VLX30T
Interconnector
Data
36 bits
Data
8x16
bits
Board with analog
and clock distribution
components
QDR II SRAM
512K x 36
Board with
digital and
IPMI components
inhib
it
Power
supply
JTAG
AD9510
AD9513
Clocks 1-2
Buffers
Data
8 bits
Clocks 3-6
Signal conditioning
band-pass filters
ADC
1-4
AMC connector B+
IDT71P74604
Hot -swap
switch
Functional
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ADC AD6645 - 14-bit, 80 – 105 MSPS,
conversion time 4 maximum clocks,
FPGA - Virtex 5 XC5VLX30T
QDR II SRAM IDT71P74604 18 Mb, 250 MHz
EEPROM XCF16P for FPGA – two configurations
IPMI
Clock distribution AD9510, AD9513 – configured by FPGA
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clock distribution stability better than 5 ps
2 different clocks for ADC 1-4 and ADC 5-8
clocks configured by FPGA
Buffers – 74LCX574 – for latching data from converters
Interface
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8x analog signal 50-100 MHz through signal
conditioning connected to ADC
6x clock up to 100 MHz, LVDS bus
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2 of them connected to FPGA and ADC (user can choose clock for
ADCs)
4 clocks connected to FPGA, LVDS bus
IPMBus
Data 8 bits bus
Stage of work
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All schematics are done
Layouts are expected to be finished by the
end of January
The prototype board is expected to be started
by the end of February
Tests of the protoype board are expected to
be done by the and of April
Thank You for Your attention