Transcript DataThroughput.ppt

Data Throughput
Data Throughput
• 16 bit ADC values => 2 bytes/ADC
• ADC converting at 1 MHz (digital CDS will provide 16 bit values at
1 MHz also)
• Each ADC has own path to FPGA.
• ADC clock must operate at 16 MHz
• 8 separate data streams per clock board FPGA
• FPGA receives data at 2 Mbytes/s x 8 data streams = 16 Mbytes/s
• There are 8 sets of boards all collecting 16 Mbytes/s of data
• 128 Mbytes/s (1024 mbps) must be sent to host computer if there
is no buffering
Interfaces
• USB 2.0: Maximum transfer 480 mbps
• Gigabit Ethernet: 1000 mbps
• We need multiple data streams
– 2 data streams for gigabit ethernet
– 3 data streams for USB 2.0
• Still need to investigate Rocket I/O