Transcript FPGA Basics
Introduction to FPGA’s FPGA (Field Programmable Gate Array) – ASIC chips provide the highest performance, but can only perform the function they were designed for. – FPGA’s can be reprogrammed using HDL’s or other design methods to implement a incredible variety of functions Allow for efficient and cost-effective prototyping Cost of FPGA chips is very low compared to ASIC’s because they are not specialized for a specific task FPGA: Configurable Logic Blocks Essential FPGA component Each CLB can be reprogrammed to implement a basic sequential or combinational circuit Create array of CLB’s – At intersection of wires are switches – Form switching matrix FPGA: Configurable Logic Blocks Two 16x1 RAM blocks 8x1 RAM block 2 Edge-triggered D flipflops Multiplexers used to configure interconnects Newer FPGA’s provide other additional hardware features FPGA: Configurable Logic Blocks RAM blocks act as Look Up Tables Used to implement combinational functions By using all 3 LUT’s, can implement any Boolean function of 5 variables FPGA: Switching Network PSM: programmable switching matrix configured to connect vertical and horizontal wires Singles: connect adjacent PSMs Doubles: connect every other PSM (traverses 2 CLBs) Quad: traverses 4 CLBs Global: run entire length of chip. Use tristate buffers and can be used as buses shared by several CLBs Purpose: allows signals to be routed through fewer switching points Global nets: low-skew signal network for high fan-out signals (clocks and reset signals) FPGA Design Flow XILINX FPGA comparison Highest DSP Performance per Family Largest Family Member Highest # of MACs Max Clock Rate Virtex-4SX55 512* 500 MHz Virtex-4FX140 192* 500 MHz Virtex-4LX200 96* 500 MHz Virtex-II Pro100 444** 300 MHz Spartan-35000 104** 185 MHz * Using XtremeDSP slices only (18x18 multiply, 48-bit accumulator) ** Using MACs built from hard embedded 18x18 multipliers only Feature Virtex-II Pro Platform Spartan-3 GMACs 256 96 48 133 19 Virtex-II Block Memory* 10 MB 1.8 MB 3 MB Distributed Memory* 1.7 MB 520 KB 1.45 MB 556 104 168 Logic Cells* 125K 74K 104 K Available I/O* 1200 784 1108 Clock Speed 300+ MHz 185 MHz 220 MHz Multi-gigabit Transceivers Yes No No Embedded PowerPC Yes No No MicroBlaze Soft Processor Yes Yes Yes Dedicated 18x18 Multipliers* * Maximum Source: www.xilinx.com Reference(s) Introductory VHDL From Simulation to Synthesis, Sudhakar Yalamanchili, Prentice-Hall, Inc., 2001.