Transcript Mixed-Signal Option for the Teradyne Integra J750 Test System

Mixed-Signal Option for
the Teradyne Integra
J750 Test System
May08-12
Emily Evers
Vincent Tai
1
Definitions
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ADC – Analog-to-Digital Converter
DAC – Digital-to-Analog Converter
Op-amp – Operational amplifier
DIB – Device Interface Board
DUT – Device under Test
IG-XL – Software used by Teradyne for the J750 tester
INL – Integral Nonlinearity
DNL – Differential Nonlinearity
IMD – Intermodulation Distortion
2
Contents
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Requirements Specification
Project Plan
Design Method
Engineering Specification
Detailed Design
3
Problem Statement
The Teradyne system has been updated to
allow for analog circuits to be tested, but
there are no working test procedures for ADC,
DAC and Op-Amps.
4
Concept Sketch
Daughterboard
Socket Converter
Teradyne J750
IG-XL Software
5
System block diagram
IC Interface
Devices
Documentation
IG-XL Software
Testing
6
System Description
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Devices
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Analog-to-Digital (ADC)
Digital-to-Analog (DAC)
Op-Amp
IC Interface
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Device Interface Board (DIB)
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Connects daughter board to tester via pogo pins
Daughter Board
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Connects device to DIB
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System Description
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IX-GL Software
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Test Plan
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Pin and Channel Map
AC and DC Specs
Timing
Pattern
Testing
Documentation
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Operating Environment
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The room environment needs to be kept at a
consistent temperature of 30°C ± 3°
Electrostatic discharge wrist bands must be
worn when using the tester
Access code
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Users
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Electrical and Computer Engineering Faculty
Graduate Students interested in IC testing
Students in EE 418: High Speed System
Engineering Measurement and Testing
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User Interface
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IG-XL software
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Functional Requirements
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Cookbook be written for the new users
Testing procedures covers the devices:
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2 Analog-to-Digital (ADC)
2 Digital-to-Analog (DAC)
Op-Amp
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Non-Functional Requirements
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Consistent temperature of 30°C ± 3°
Electrostatic discharge wrist bands must be
worn when using the tester
Documentation in English
Test program for devices and similar ones
Cookbook for specified devices
Easy to trouble shooting
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Market Survey
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Teradyne website
Previous team’s website
Teradyne lab manuals
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Deliverables
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DIB and Daughterboard Mapping
IG-XL code for each device
Completed testing for all devices
Documentation for all devices
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Work Breakdown structure
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Review Status
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Previous work
Teradyne Training Material
IC Interface
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Daughter Board
DIB
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Work Breakdown Structure
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Test Plan Development
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Documentation
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Create IG-XL code for testing devices
Debug previous code
Add current limits
New test plans
Execute testing
Create Mixed-Signal Option Cookbook
Create maps for daughter board, DIB and socket
converters
Reporting
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Resource Requirements
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Resource Team
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Faculty Advisor: Dr. Weber
Course Coordinator: Dr. Smith
Team effort
Review
Status
IC Interface
Test plan
developing
Testing
Documentation
Reporting
Total hours
Emily Evers
16.75
17
50
32
30
31.5
177.25
Vincent Tai
15
18.5
50
32
30
15
160.5
Total
31.75
35.5
100
64
60
46.5
337.75
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Resource Requirements
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Financial requirements
Item
Cost
Materials
Poster
$35.00
Devices
$130.00
Daughterboard
$200.00
Subtotal
$365.00
Emily Evers
$1772.50
Vincent Tai
$1605.00
Subtotal
$3377.50
Labor($10.00/hr)
Total
$3742.50
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Project Schedule
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Deliverable schedules
Deliverables
Project Plan
Website
Design Report
Final Report
Poster
Date
10/2/2007
10/2/2007
12/4/2007
April 2008
April 2008
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Project Schedule
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Projected Deliverable Schedules
Deliverable
IC Interface
IG-XL development
Testing
Documentation
Projected Date
October 2007
December 2007
March 2008
April 2008
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Project schedule
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Accomplishment
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Interface Mapping
AD 5447 Progress
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Accomplishment
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D Flip-Flop Test
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Risk And Risk Management
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Risk:
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Problems learning program
Limited team members
Risk Management:
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Read Teradyne manuals and previous groups
documentation
Time management
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Design Method
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Top-Down Design
Inputs
Process
Outputs
Parts
Results
Cookbook
ADC
DAC
Input/Output Signals
Op-Amp
Calculations
AD7892
AD7470
AD5440
AD5447
AD823
Hardware
Software
IG-XL Program
ADC & DAC
Op-Amp
INL & DNL
Bandwidth
Offset Voltages
Intermodulation Tests
Interfaces
J750 Tester
DIB
Daughterboard
Socket converter
Computer
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Input Requirements &
Specifications
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Input Requirements
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Devices
 ADC
 DAC
 Op-Amp
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Input Specifications
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ADC
 10 bit
 12 bit
DAC
 10 bit
 12 bit
Op-Amp
 High Speed
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Inputs
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Detailed Design
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ADC
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Op-Amp
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AD7892
AD7470
AD823
DAC
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AD5447
AD5440
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Inputs
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Detailed Design
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AD7892
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12 bit
Runs off of single 5V supply
Signal-to-noise ratio of 70dB
Conversion time of 1.47us
Sampling rate of 500 KSPS
Cost is $15.45
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Inputs
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Detailed Design
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AD7470
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10 bit
Single volt supply voltage can range from 2.7V to
5.25V
Sampling rate of 1.75 MSPS
Wide input bandwidth
No pipeline delay
Cost is $3.53
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Inputs
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Detailed Design
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AD823
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Houses two amplifiers
16 MHz rail-to-rail FET amplifier
Cost is $2.63 with free sample available
Operates on single or dual power supply
Drive capability of 500pF
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Inputs
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Detailed Design
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AD5447
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12 bit
Update rate of 21.3 MSPS
Settling time of 35ns
10 MHz multiplying bandwidth
Cost is $9.00
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Inputs
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Detailed Design
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AD5440
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10 bit
Update rate of 21.3 MSPS
Settling time of 35ns
10 MHz multiplying bandwidth
Cost is $6.90
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Outputs
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Requirements
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Test Results
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Specifications
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Input Signals
Output Signals
Calculations
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Outputs
HLHLHL
ADC
HLHLHL
DAC
Op-Amp
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Outputs
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Detailed Design
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ADC and DAC
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INL
DNL
Op-Amp
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Bandwidth
Offset Voltages
Intermodulation Test
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Outputs
Detailed Design
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INL = Actual Output - Expected Output
Integral Nonlinearity
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Measure of an error of a
point with respect of the
user defined transfer
function
Analog Output 0 - 5V
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Actual Output
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Expected Output
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Digital Input 0x00 - 0xFF
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Outputs
Detailed Design
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Actual
Step
Size
DNL
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Comparison of the step
size error of an actual
output to the expected
output
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Analog Output 0 - 5V
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Exected Step
Size
DNL=Actual Step Size - Expected Step
Size
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Digital Input 0x00 0xFF
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Outputs
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Detailed Design
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Bandwidth
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Small Signal
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Open Loop
 Point where the
output is equal to 0dB
Closed Loop
 Point where there is a
drop of 3dB
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Outputs
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Detailed Design
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Bandwidth
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Large Signal
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Slope of output is called
slew rate
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Outputs
Detailed Design
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Offset Voltage
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Difference between the
actual output and the
expected output at the
zero point
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Analog Output 0 - 5V
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•
Actual Output
Expected Output
Digital Input 0x00 - 0xFF
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Outputs
Detailed Design
Intermodulation Test
Determines distortion
caused by slight
variations gain vs.
amplitude
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IM  20log
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
60dB
MagM 1M 2 2  MagM 2M 1 2 
MagM 1
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
0
50
F2 - F1
F2
F2 + F1
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F1
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0d
B
MAGNITUDE
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100
150
200
250
FREQUENCY
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User Interface
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Requirements
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Mixed-Signal Cookbook
IG-XL
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Specifications
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Mixed-Signal Cookbook
 Written in English
 Easy-to-use
IG-XL Program
 Create test programs
with adequate
commenting
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Software
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Requirements
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IG-XL
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Specifications
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Pin & Channel Maps
AC & DC Specs
Time Sets
Levels
Test Instances
Procedures
Flow Table
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Software
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Detailed Design
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Data for IG-XL worksheets is gathered from the
datasheets for the DUT
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Software
AC specs
Time Sets
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Hardware
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Requirements
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Teradyne J750
Device Interface
Computer
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Specifications
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DIB
Daughterboard
Socket Converter
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Hardware
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Detailed Design
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Create mapping from DIB to DUT
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Map DIB to Daughterboard
Map Daughterboard to Socket Converter
Map Socket Converter to DUT
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Hardware
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Detailed Design
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Interface Mapping
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Hardware
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Testing
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Requirements
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Cookbook use
 Team Members
 Faculty Advisor
 Students
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Specifications
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Ease of manipulation for
different models
Ease of changing desired
calculations
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Thank You
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Questions?
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