Mixed-Signal Option for the Teradyne Integra J750 Test System
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Transcript Mixed-Signal Option for the Teradyne Integra J750 Test System
Mixed-Signal Option for
the Teradyne Integra
J750 Test System
May08-12
Emily Evers
Vincent Tai
1
Definitions
ADC – Analog-to-Digital Converter
DAC – Digital-to-Analog Converter
Op-amp – Operational amplifier
DIB – Device Interface Board
DUT – Device under Test
IG-XL – Software used by Teradyne for the J750 tester
INL – Integral Nonlinearity
DNL – Differential Nonlinearity
IMD – Intermodulation Distortion
2
Contents
Requirements Specification
Project Plan
Design Method
Engineering Specification
Detailed Design
3
Problem Statement
The Teradyne system has been updated to
allow for analog circuits to be tested, but
there are no working test procedures for ADC,
DAC and Op-Amps.
4
Concept Sketch
Daughterboard
Socket Converter
Teradyne J750
IG-XL Software
5
System block diagram
IC Interface
Devices
Documentation
IG-XL Software
Testing
6
System Description
Devices
Analog-to-Digital (ADC)
Digital-to-Analog (DAC)
Op-Amp
IC Interface
Device Interface Board (DIB)
Connects daughter board to tester via pogo pins
Daughter Board
Connects device to DIB
7
System Description
IX-GL Software
Test Plan
Pin and Channel Map
AC and DC Specs
Timing
Pattern
Testing
Documentation
8
Operating Environment
The room environment needs to be kept at a
consistent temperature of 30°C ± 3°
Electrostatic discharge wrist bands must be
worn when using the tester
Access code
9
Users
Electrical and Computer Engineering Faculty
Graduate Students interested in IC testing
Students in EE 418: High Speed System
Engineering Measurement and Testing
10
User Interface
IG-XL software
11
Functional Requirements
Cookbook be written for the new users
Testing procedures covers the devices:
2 Analog-to-Digital (ADC)
2 Digital-to-Analog (DAC)
Op-Amp
12
Non-Functional Requirements
Consistent temperature of 30°C ± 3°
Electrostatic discharge wrist bands must be
worn when using the tester
Documentation in English
Test program for devices and similar ones
Cookbook for specified devices
Easy to trouble shooting
13
Market Survey
Teradyne website
Previous team’s website
Teradyne lab manuals
14
Deliverables
DIB and Daughterboard Mapping
IG-XL code for each device
Completed testing for all devices
Documentation for all devices
15
Work Breakdown structure
Review Status
Previous work
Teradyne Training Material
IC Interface
Daughter Board
DIB
16
Work Breakdown Structure
Test Plan Development
Documentation
Create IG-XL code for testing devices
Debug previous code
Add current limits
New test plans
Execute testing
Create Mixed-Signal Option Cookbook
Create maps for daughter board, DIB and socket
converters
Reporting
17
Resource Requirements
Resource Team
Faculty Advisor: Dr. Weber
Course Coordinator: Dr. Smith
Team effort
Review
Status
IC Interface
Test plan
developing
Testing
Documentation
Reporting
Total hours
Emily Evers
16.75
17
50
32
30
31.5
177.25
Vincent Tai
15
18.5
50
32
30
15
160.5
Total
31.75
35.5
100
64
60
46.5
337.75
18
Resource Requirements
Financial requirements
Item
Cost
Materials
Poster
$35.00
Devices
$130.00
Daughterboard
$200.00
Subtotal
$365.00
Emily Evers
$1772.50
Vincent Tai
$1605.00
Subtotal
$3377.50
Labor($10.00/hr)
Total
$3742.50
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Project Schedule
Deliverable schedules
Deliverables
Project Plan
Website
Design Report
Final Report
Poster
Date
10/2/2007
10/2/2007
12/4/2007
April 2008
April 2008
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Project Schedule
Projected Deliverable Schedules
Deliverable
IC Interface
IG-XL development
Testing
Documentation
Projected Date
October 2007
December 2007
March 2008
April 2008
21
Project schedule
22
Accomplishment
Interface Mapping
AD 5447 Progress
23
Accomplishment
D Flip-Flop Test
24
Risk And Risk Management
Risk:
Problems learning program
Limited team members
Risk Management:
Read Teradyne manuals and previous groups
documentation
Time management
25
Design Method
Top-Down Design
Inputs
Process
Outputs
Parts
Results
Cookbook
ADC
DAC
Input/Output Signals
Op-Amp
Calculations
AD7892
AD7470
AD5440
AD5447
AD823
Hardware
Software
IG-XL Program
ADC & DAC
Op-Amp
INL & DNL
Bandwidth
Offset Voltages
Intermodulation Tests
Interfaces
J750 Tester
DIB
Daughterboard
Socket converter
Computer
26
Input Requirements &
Specifications
Input Requirements
Devices
ADC
DAC
Op-Amp
Input Specifications
ADC
10 bit
12 bit
DAC
10 bit
12 bit
Op-Amp
High Speed
27
Inputs
Detailed Design
ADC
Op-Amp
AD7892
AD7470
AD823
DAC
AD5447
AD5440
28
Inputs
Detailed Design
AD7892
12 bit
Runs off of single 5V supply
Signal-to-noise ratio of 70dB
Conversion time of 1.47us
Sampling rate of 500 KSPS
Cost is $15.45
29
Inputs
Detailed Design
AD7470
10 bit
Single volt supply voltage can range from 2.7V to
5.25V
Sampling rate of 1.75 MSPS
Wide input bandwidth
No pipeline delay
Cost is $3.53
30
Inputs
Detailed Design
AD823
Houses two amplifiers
16 MHz rail-to-rail FET amplifier
Cost is $2.63 with free sample available
Operates on single or dual power supply
Drive capability of 500pF
31
Inputs
Detailed Design
AD5447
12 bit
Update rate of 21.3 MSPS
Settling time of 35ns
10 MHz multiplying bandwidth
Cost is $9.00
32
Inputs
Detailed Design
AD5440
10 bit
Update rate of 21.3 MSPS
Settling time of 35ns
10 MHz multiplying bandwidth
Cost is $6.90
33
Outputs
Requirements
Test Results
Specifications
Input Signals
Output Signals
Calculations
34
Outputs
HLHLHL
ADC
HLHLHL
DAC
Op-Amp
35
Outputs
Detailed Design
ADC and DAC
INL
DNL
Op-Amp
Bandwidth
Offset Voltages
Intermodulation Test
36
Outputs
Detailed Design
INL = Actual Output - Expected Output
Integral Nonlinearity
Measure of an error of a
point with respect of the
user defined transfer
function
Analog Output 0 - 5V
Actual Output
•
Expected Output
Digital Input 0x00 - 0xFF
37
Outputs
Detailed Design
Actual
Step
Size
DNL
Comparison of the step
size error of an actual
output to the expected
output
•
Analog Output 0 - 5V
Exected Step
Size
DNL=Actual Step Size - Expected Step
Size
Digital Input 0x00 0xFF
38
Outputs
Detailed Design
Bandwidth
Small Signal
Open Loop
Point where the
output is equal to 0dB
Closed Loop
Point where there is a
drop of 3dB
39
Outputs
Detailed Design
Bandwidth
Large Signal
Slope of output is called
slew rate
40
Outputs
Detailed Design
Offset Voltage
Difference between the
actual output and the
expected output at the
zero point
Analog Output 0 - 5V
•
Actual Output
Expected Output
Digital Input 0x00 - 0xFF
41
Outputs
Detailed Design
Intermodulation Test
Determines distortion
caused by slight
variations gain vs.
amplitude
IM 20log
60dB
MagM 1M 2 2 MagM 2M 1 2
MagM 1
0
50
F2 - F1
F2
F2 + F1
F1
0d
B
MAGNITUDE
100
150
200
250
FREQUENCY
42
User Interface
Requirements
Mixed-Signal Cookbook
IG-XL
Specifications
Mixed-Signal Cookbook
Written in English
Easy-to-use
IG-XL Program
Create test programs
with adequate
commenting
43
Software
Requirements
IG-XL
Specifications
Pin & Channel Maps
AC & DC Specs
Time Sets
Levels
Test Instances
Procedures
Flow Table
44
Software
Detailed Design
Data for IG-XL worksheets is gathered from the
datasheets for the DUT
45
Software
AC specs
Time Sets
46
Hardware
Requirements
Teradyne J750
Device Interface
Computer
Specifications
DIB
Daughterboard
Socket Converter
47
Hardware
Detailed Design
Create mapping from DIB to DUT
Map DIB to Daughterboard
Map Daughterboard to Socket Converter
Map Socket Converter to DUT
48
Hardware
Detailed Design
Interface Mapping
49
Hardware
50
Testing
Requirements
Cookbook use
Team Members
Faculty Advisor
Students
Specifications
Ease of manipulation for
different models
Ease of changing desired
calculations
51
Thank You
Questions?
52