Animation of Important Concepts in Parallel Computer Architecture

Mohit Gambhir 1 Edward F. Gehringer 1, 2 Yan Solihin 2 1 Department of Computer Science 2 Department of Electrical & Computer Engineering North Carolina State University {mgambhi, efg, solihin}@ncsu.edu

Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin June 9, 2007

Outline

    Introduction Creation of animations The animations   Cache coherence Protocol comparison    Memory consistency problem Consistency models Prototype components Conclusions and future work June 9, 2007 Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin

Introduction

  Motivation    As uniprocessor architectures approach their physical limits, multicore designs are becoming common.

Multiprocessor architectures affect the programming model. Difficult to find illustrations of parallel architecture concepts.

Suite of animations covering concepts like cache coherence, memory consistency.

June 9, 2007 Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin

Creation of animations

 Created by students, refined by the authors and professionally formatted.

    Students were given assignments that covered scenarios highlighting the key aspects of a protocol, algorithm or a model. Student work was peer-reviewed by other students. The most highly rated submissions were checked for technical correctness by the instructor. The animations were professionally formatted by the graphic designers at NCSU Distance Education Learning Technology Applications.

Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin June 9, 2007

Signing up for a First-Round Topic June 9, 2007 Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin Students select a topic from a list.

  Several students are al lowed to select the same topic, But the number of slots is limited.

The Review Rubric

June 9, 2007 Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin

After the Initial Review

    Resubmission phase. 2–7 days to revise work in response to reviewer comments.

Grading phase. 3–7 days to make final comments and assign scores.

Review of review phase. Students review each other’s reviews.

After this, the best submissions are chosen for inclusion in the suite.

June 9, 2007 Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin

MSI cache coherence protocol

    A bus-based shared memory system with 3 processors.

P

1 reads a line which exists in P 3 ’s cache in the Modified state.

Read involves a sequence of three operations shown as a sub-trace connected to the main trace. Three operations shown on three consecutive slides.

Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin June 9, 2007

   

Full bit-vector directory-based protocol

A distributed shared memory system.

P

3 writes to a line that is in the shared state.

Write involves a sequence of 4 operations. The screenshot shows the third of those operations where the home directory sends an Inv and a ReplyId message to P 1 and P 3 respectively. June 9, 2007 Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin

More cache coherence animations

 Other cache coherence animations in the suite:   Two-state write-through, write-invalidate Simplified SCI June 9, 2007 Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin

MESI vs. MOESI

   A comparison between the two cache-coherence protocols.

P

2 reads a line that is in P 1 ’s cache in the Modified state.

The snapshot highlights the difference between the two protocols. Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin June 9, 2007

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Firefly vs. Dragon

A comparison between two update-based protocols. P 2 writes to a line that is in the shared state. The snapshot highlights the difference between the two protocols. Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin June 9, 2007

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Release consistency

The grid on top shows the sequence of memory accesses by four processors. Horizontal axis represents time.

The values shown alongside the read operations are the ones that are acceptable under release consistency. Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin June 9, 2007

Prototype components

  A library of Power Point components that can be used to create more animations. Widgets for creating processors, caches, bus, memory locations etc. June 9, 2007 Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin

Conclusions and future work

    We have a suite of animations for teaching parallel computer architecture.

Freely usable by anyone for teaching. In Fall 2007, we plan to add animations of additional protocols and models.

If you teach these topics, we will gladly supply you with components and review software. Help us add to our library!

Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin June 9, 2007

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Peterson’s algorithm

The snapshot is taken from an animation that illustrates the problem that non-sequentially consistent memory imposes on Petersons’s algorithm. Step-by-step execution of code on two processors. Reordering of memory operations causes the two processors to enter the critical section simultaneously. Animation of Important Concepts in Parallel Computer Architecture Gambhir, Gehringer & Solihin June 9, 2007