Transcript Front-end Electronics for the Alice Detector Kjetil Ullaland

Front-end Electronics
for the Alice Detector
Kjetil Ullaland
Department of Physics and Technology, University of Bergen, Norway
NFR meeting, University of Bergen 19.10.2005
The ALICE Experiment
Time Projection Chamber
• Main tracking detector
• Provides particle id and
momentum
• Detection of charged
particles by ionization of the
gas volume
• 2-dimensional read-out at
end-caps, drift time gives 3rd
coordinate
• 2 x 18 sectors
• 4356 Front-End Cards,
serving roughly 560000
channels
•
simulated low multiplicity event
•
designed for dNch/dy = 8000 : ~ 20000 tracks
TPC Front-end Electronics
36 TPC Sectors, served by 6 readout subsystems, Readout Control Unit (RCU)
in total 216 RCUs and 4356 Front-End Cards
FEC
25
128 ch
ON DETECTOR
COUNTING ROOM
ALTRO bus
DETECTOR
( 200 MB / s )
FEC
14
FEC
13
128 ch
128 ch
Branch B
FEC
12
128 ch
FEC
2
FEC
1
128 ch
128 ch
Branch A
Local
Slow- Control
(I2C-serial link)
ALTRO
Bus
Interface
Monitoring
and
Safety
Module
Data
assembler
RCU
SIU
interface
DCS
board
Trigger
interface
Detector Data Link
( 200 MB / s )
Data Acquisition
Incl. HLT-RORC
Ethernet
( 1 MB/s )
Detector Control
System
TTC optical Link
(Clock, L1 and L2 )
Trigger and Clock
System
Readout Control Unit
• Consists of:
– the RCU motherboard
– a DCS (Detector Control System) board embedded computer
– a SIU (Source Interface Unit) mezzanine card.
• The system makes use of SRAM based FPGAs.
– Flexibility & options for reconfiguration
• Major concerns are
– Radiation tolerance of the electronics.
– The huge data rate of the system (up to 710 GB/s without zero-suppression).
• Low-level data rate lowered by:
– A trigger based system. (Only read out data when there are valid data)
– Compressing algorithms on the ALTRO chip on the Front End Card.
Readout Control Unit
SIU DCS
RCU
Readout Control Unit
Data Acquisition
System
Trigger
System
Optical link
2 Gb/s
Detector Control
System
Ethernet
10Mb/s
Optical link
DCS-board
SIU-card
embedded computer
TTCrx
ASIC
t FPGA
Altera
w/ ARM cpu
Level 1 trigger
serial B channel
Bank 0
Bank 1
Bank 2
Bank 3
FLASH mem
w/ Linux
32 bit bus
RCU motherboard
Bank 0
Xilinx
Actel FPGA 32 bit/50 MHz Virtex-II Pro
FPGA
Radiation tolerant
SelectMap IF
FPGA
(Actel)
Bank 1
Bank 2
Bank 3
FLASH
jtag
jtag
jtag
2x40 bit bus
Front End Cards
Readout Control Unit
• In ALICE, complete RCUs are to be used in:
– TPC sub-detector
– PHOS sub-detector
– FMD sub-detector
– EMCAL sub-detector
• DCS board used in ALICE TRD sub-detector as well.
• Other experiments have also expressed an interest to use
the RCU.
Detector Control System
Supervisory Layer
(PC’s with graphical user interface)
Front-End Device Interface (FED)
Control Layer
(PC’s with communication software)
Front-End Electronics Interface (FEE)
Field Layer
(216 RCUs with DCS Boards)
DCS Board Embedded Computer
• Single board computer used
in several detectors in ALICE
• Combines LINUX operating
system with a Programmable
Logic Device (PLD)
• Device drivers introduces an
abstraction layer, decoupling
software from hardware.
• The conceptual design is a co-development between Bergen
and Heidelberg.
• Final hardware designed and produced in Heidelberg.
• Firmware/software co-designed by Bergen and Heidelberg
RCU Motherboard
• RCU motherboard:
– Prototype developed by Bergen.
– Final version a co-development
between Bergen and CERN.
Mass production ongoing now!
– Firmware is a co-development
between Bergen and CERN
• RCU motherboard is in the
data readout chain in the TPC
detector.
• RCU motherboard host basic controlling functionalities for the FECs
• Irradiation tolerance is critical!
Radiation Effects
• Single Event Effects (SEE)
p
– Single Event Latch-up (SEL)
– Single Event Upset (SEU)
– Single Event Functional Interrupt
(SEFI)
Si
• Cumulative Effects
– Total ionizing dose (TID)
– Displacement damage
SEE : Single event effects are radiation induced errors due to a single charged
particle depositing energy through ionization of the material.
Programmable Devices
• FPGA: Field Programmable Gate Array
– Introduced in 1985 by Xilinx, Inc.
– Array of programmable logic blocks
– Logic gates, LUTs, flip-flops etc
•
SRAM based Configuration Memory
–
–
–
–
Controls behaviour of the logic blocks
SEE major concern
Sensitive to ionizing particles
Configuration memory may change
content: 1  0 / 0  1
• Flash based Configuration Memory
– Cumulative effects is a concern
Simulations of Radiation Enviroment
• Main particles of concern are hadrons
of energy above 10-20 MeV (nuclear
interactions)
• Total dose for 10 Alice years is
5.7 Gy or ~0.6kRad
• Expected hadron flux ~ 800
hadrons/cm2-s (worst case)
(Morsch, Sandoval, Tsiledakis GSI)
Peak at 100-200 MeV
Irradiation Tests at TSL and OCL
•
SRAM based FPGAs:
–
–
–
•
FLASH based FPGAs:
–
•
Xilinx Virtex-II Pro 7 (RCU)
Altera APEX20K (RCU old prototype)
Altera EPXA1-ARM (DCS card)
Actel ProAsic APA075 (RCU)
Integration test
–
–
DCS embedded computer
Full FEE readout Chain
•
Discrete components
•
Proton irradiation
–
–
•
Energy: ~29, 38 & 180 MeV
Flux 106-107 [p/cm2/s]
Neutron irradiation
–
–
Energy: 50, 95, 180 MeV
Flux: 103 – 104 [n/cm2/s]
Results
Xilinx & Altera FPGA:
(@ 180 MeV)
Actel FPGA:
• Survived dose of ~ 7 kRad. Expected for ALICE: ~ 0.6 kRad
Conclusions of the Irradiation Tests
• SRAM based FPGAs:
–
–
–
–
–
–
Error rate at the limit of what can be tolerated
Radiation tolerant schemes
Detect SEUs instantaneously
Real-time read-back of configuration memory
Active partial reconfiguration (supported by Xilinx)
Error detection and correction techniques
• Actel FPGA (Flash):
– Dose results satisfying
– (exp: ~ 0.6 kRad , res: ~ 7 kRad)
Active reconfiguration
• Functionality of both DCS and RCU board can
experience errors due to radiation effects in the
FPGAs
• Simple reloading of configuration data causes
downtime and is thus not applicable to RCU board
(interruption of data-flow)
-
Active error detection and reconfiguration
scheme using an FPGA capable of refreshing
firmware w/o interrupting operation
Altera FPGA
w/ ARM cpu
Bank 0
Bank 1
Bank 2
Bank 3
FLASH mem
w/ Linux
Active Partial Reconfiguration “scrubbing”
DCS-board
RCU-board
Bank 0
Xilinx
Virtex-II Pro
FPGA
SelectMap IF
Radiation tolerant
FPGA
(Actel)
Bank 1
Bank 2
Bank 3
FLASH
Preliminary test results with scrubbing
(flux ~1.5*107 p/cm2-s)
32 Bit Lines, RED = Errors
Plain Shift Register
• SEFI test with Xilinx
• Virtex-II Pro FPGA
• Scrubbing
• started after ~200 s:
• Errors are corrected
• Continuously
• ~sec to “scrubb” full
• device
• Improved to ~ms
0
60
120
180
240
Test carried out by G. Tröger, KIP
seconds 360
HLT-RORC
HLT-RORC
•
•
•
•
•
The HLT-RORC is the low-level part of the High Level Trigger.
Main purpose is to do online processing of the data incoming data.
Found on each of the Front-end Processors on the HLT Computer Farm,
receiving data directly from the RCU.
A dual purpose co-processor is being implemented which alternatively can do:
– Hough-transform of collected raw-data.
– Cluster-finding
Implemented with a Xilinx
Virtex-4 FPGA and a
PCI interface
HLT-RORC
• Developed by Bergen:
– Firmware for the Clusterfinder
– Conceptual Software for the Clusterfinder and the
Hough-transform
– DMA controller with interrupt handling
– Prototype HLT-RORC PCI card for firmware/software
development and testing
• Engineering prototype of HLT-RORC mezzanine card
developed by KIP in Heidelberg.
Status
• Mass production of RCU motherboard and DCS board
embedded computer has started.
• Firmware on RCU, both on the main FPGA and on the support
FPGA soon ready as final engineering prototype.
• Firmware and Software on DCS board soon ready as final
engineering prototype.
• HLT RORC engineering prototype finished.
• HLT RORC firmware/software is under development.
Outlook
• More irradiation tests of FEE are scheduled.
– Discrete components
– Integration tests
• Assembling of Front End Cards in the TPC end plates at CERN
December 2005 – February 2006.
• Commissioning of TPC RCU system from February-August 2006.
• TPC Electronics will be installed in the ALICE pit September 2006.
• HLT RORC: Integrate existing firmware modules.
• To be fully operative by commissioning of ALICE detector in 2007.
Acknowledgements
•
J. Alme, B. Pommeresche, M. Richter, S. Bablok, D. Larsen, B. H. Straume, O. Torheim, K.
Ullaland, D. Röhrich
–
•
K. Røed, H. Helstrup
–
•
GSI, Gesellschaft für Schwerionenforschung, Darmstadt, Germany
T. Alt, G. Tröger, D. Gottschalk, V. Lindenstruth, H. Tilsner
–
•
Center for Technology Transfer and Telecommunications, University of Applied Science Worms, Germany
U. Frankenfeld
–
•
Institute of Communication Engineering, University of Applied Sciences Cologne, Germany
R. Keidel, Ch. Kofler
–
•
The Svedberg Laboratory, Uppsala University
T. Krawutschke
–
•
Department of Physics, University of Oslo
A. Prokofiev
–
•
Faculty of Engineering, Bergen University College, Norway
B. Skaali, E. Olsen, J. Wikne
–
•
Department of Physics and Technology, University of Bergen, Norway
Kirchhoff Institute of Physics, University of Heidelberg, Germany
B. Mota, R. Campagnolo, C. Gonzalez Gutierrez, A. Junique, L. Musa
–
CERN, European Organization for Nuclear Research, Geneva, Switzerland
TPC Front-end Electronics
TPC-Subsystem as used in radiation beam test in Uppsala April 2005
- RCU system used in TPC sub-detector and in PHOS sub-detector (different Front-end Cards!)
- Close to interaction point
- Exposed to radiation