Extending FPGA Verification Through The PLI Charles Howard Senior Research Engineer Southwest Research Institute San Antonio, Texas (210) 522-3419 [email protected].
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Transcript Extending FPGA Verification Through The PLI Charles Howard Senior Research Engineer Southwest Research Institute San Antonio, Texas (210) 522-3419 [email protected].
Extending FPGA Verification Through
The PLI
Charles Howard
Senior Research Engineer
Southwest Research Institute
San Antonio, Texas
(210) 522-3419
[email protected]
1
Background
Verilog is a hardware description language for digital logic
design (FPGA/ASIC/PLD)
Typical usage
– Design
End item design description (RTL for synthesis)
– Verification
Modeling input interfaces (providing proper data/control
relationships)
Generation of test stimuli, esp. for low-level verification
activities.
Robust & simple first order DV with standard tools
– Not adequate with growing complexity, multiple devices
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Low-level Verification
Results of this first order modeling are often verified by
visual means
– Finite limitation on the amount of transactions that can be
verified visually
Rudimentary checking of interface protocols in Verilog
models
– Repetitive pattern detection
– Interface timing
Verilog checkers increase verification capabilities
tremendously
– Directed tests are excellent for nominal function
– Perfect for small number of scenarios
It is at this point that the real strength of Verilog is
revealed – the programming level interface (PLI).
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The Verilog PLI
The Programming Language Interface is a procedural
interface between Verilog simulation and other software
programs
– Verilog models can invoke external program during
simulation
Accessibility to every attribute within the simulation
structure
Capability to read and/or modify any value in the
simulation
Flexibility to perform any simulation task
– Initializing memories at simulation start
– Verifying end of simulation results.
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A Few PLI Applications
PLI can be used to link any type of application to the
simulation
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Delay calculators
Custom displays
C language models
Hardware modelers
Co-simulation environments
Reading test vector files
Custom user interfaces
Design debug utilities
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PLI Implementations
C programs can be tied through the PLI to Verilog shell
models
C programs then used to:
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Dynamically generate test stimuli
Check design outputs
Scoreboard non-linear data flows
Incorporate random features
Layered approach
– Sequences and scenarios
Random and directed
– Coverage
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PLI Advantages
Simulations do not need to be limited
– Time, complexity or randomness
Extended to reflect the real world
More simulation cycles can occur
Capability to randomize each test
Coverage
– Regression tests
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PLI Goal
In short, the PLI allows the designer to build a robust
virtual test bench that allows the functional interaction of
hardware and software to first be characterized without
lab space.
– Recent experiences (what I have learned in the customer’s
lab)
Flow Control from multiple sources
FSW access order
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Randomization
An immense number of HW/SW interactions can be
characterized for flaws
Using random and directed test techniques, functional
verification of the logic design can be extended far
beyond first order techniques.
Resulting design is much more robust and likely to
function when moved into silicon.
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Our approach
PLI extension of FPGA verification capabilities
Development of several key bus functional models and
PLI routines
Specific approaches and examples will be presented.
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Verification Environment
Simulations
– Each FPGA undergoes
directed simulation at the
chip level. Verifies logic,
timing, and functionality
– FPGAs are integrated into
a larger multi-FPGA,
board level simulation as
they are completed.
VC0,2
SC FIFO
VC1
Memory Control FPGA
Verifies processor ->
local bus traffic
Verifies inter-FPGA local
bus traffic
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Serial Command Processor
FPGA
Telemetry Formatting
FPGA
uP to LB FPGA
Download
able
Memory
Scratch
Memory
Health &
Status
FIFO
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Board Verification
Monitor PC
O-Scope
Ethernet
LLDC
HLDC
(Binary)
Outputs
Break-Out Box
Board Level GSE PC
Telemetry:
Parse & decode
Serial commands
MIL-STD-1553B
Differential Analog Out
Single ended Analog Out
Telemetry: Carrier, Sub-carrier,
GSE
Engineering Development Chassis
Serial commands: Primary /
Secondary / GSE
MIL-STD-1553B BC / RT
Analog Inputs 8 Differential
Analog Inputs 16 Single Ended
Resets (3), VTC_LTCH
32 Bi-Level Inputs
Digital I/O
16 GSE Bi-Level Outputs
Serial UARTInterface
Telemetry RX
COTS
SBC
+28V,
+7V
Power Supply
Serial command TX
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DUT
Backplane (PWR), Standard Bus
cPCI
GENERIC HW VERIFICATION SETUP
Ethernet
Board GSE is designed to verify
board level requirements.
– Mixture of automated and
manual measurements.
Board Test Cases have been
defined based on PFS
– Basis for PLI functions
IR&D funds for enhanced
simulation environment
– Three fundamental testing
blocks:
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SBC Based
Tests:
1. Register
Accesses /
Interrupts
2. Scratch
Memory Test
3. Downloadable
Memory
4. 1553 Shared
Memory
5. H&S FIFO
6. A/D Validation
PLI Verification Environment
cPCI
– Memory peeks / pokes, config
cycles, resets
– Exhaustive memory tests, VTC
duration testing, serial
command verification,
telemetry packet generation,
1553 traffic, access order
dependencies, etc.
SIMULATION VERIFICATION SETUP
Scoreboard
PLI
PLI
“Processor”
Based Tests:
1. cPCI
Accesses /
Interrupts
2. Scratch
Memory Test
3. Downloadable
Memory
4. 1553 Shared
Memory
5. H&S FIFO
6. A/D Validation
LLDC
HLDC
(Binary)
Outputs
Telemetry
– ASM detect, de-randomization,
frame length check
– Frame integrity, FHP check,
packet integrity, data integrity
Telecommands
Telemetry: Carrier, Sub-carrier,
GSE
Telecommands: Primary /
Secondary / GSE
MIL-STD-1553B BC / RT
MIL-STD-1553B Summit /
Shared Memory
DUT
(BOARDSIM)
A/D Digital Interface
Telecommand TX
A/D (Digital model)
Resets (3), VTC_LTCH
Virtual Backplane
Telemetry RX
Virtual
Processor
32 Bi-Level Inputs
– Inject telecommands, monitor
response
– Error injection, data integrity
(PCI side)
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BFMs
Digital I/O
16 GSE Bi-Level Outputs
Serial UARTInterface
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Results
Simulation run length
Coverage metrics
COME ON, NOW, REALLY… I’m still working on this, and
trying to bring up hardware in the lab!!!
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