Transcript A low cost DAQ card for detector R&D applications J.P.Martin, Université de Montréal • Card being developped at Université de Montréal for.

A low cost DAQ card for detector R&D applications
J.P.Martin, Université de Montréal
• Card being developped at Université de Montréal for the KOPIO collaboration at
Brookhaven National Laboratory (intended for the readout of the pre-radiator
cathode strips; 100,000 channels)
• FEATURES:
- Prototype version has VME interface => suitable for various test systems
(final KOPIO version has integrated preamps, but only LVDS readout)
- 48 channel per card, standard 6U VME form factor
- Based on 40 MS/sec 10 bit ADC
- Powerful FPGA signal processors
- Fast dual port memory pulse shape pipeline on every channel, suitable for test
TPC
- Estimated fabrication cost is less than 20 Euros/channel for the final design, in
large quantities.
- Estimated fabrication cost for the VME prototypes is about 55 Euros/channel.
J.P.Martin, ECFA_DESY
Workshop, Amsterdam, 1-4 April
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KOPIO DAQ card architecture
LVDS lines (4)
RJ45
I
n
p
u
t
Cable
from
preamps
c
o
n
n
e
v
t
o
r
(48
pairs)
300
MBauds
serial
interface
1
2
48
Differential
amplifier
Low pass
filter
Differential
amplifier
Low pass
filter
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Differential
amplifier
Low pass
filter
8 channels
40 MS/sec
10 bit
FADC
ALTERA
Cyclone
FPGA
.
.
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8 channel
40 MS/sec
10 bit
FADC
ALTERA
Cyclone
FPGA
J.P.Martin, ECFA_DESY
Workshop, Amsterdam, 1-4 April
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Trigger
Event
collector,
VME
interface
6
Synchro
System clock
2
Data flow and processing in FPGA (one channel),
(example for TPC pad readout application)
Trigger
Trigger
window
generator
(up to 4
windows,
overlap
allowed.)
Hit
detector
FADC bits
Dual
port
circular
latency
buffer
Drift time
Coarse resolving time
Data
segment
accept
logic
Accept
LVDS
Multi event buffer,
capacity:
4 events
Readout
interface
VME
Time
stamp
generator
Time vernier
Feature
extraction
logic
Amplitude
Pulse shape segment
Parameters
Size: 3.2microseconds
J.P.Martin, ECFA_DESY
Workshop, Amsterdam, 1-4 April
3
Details of the data segment accept logic
(one of 4 parallel channels)
a
Time stamp
Trigger window
begin time
a>b
a
a-b
b
Accept window begin time
Accept
a
a+b
Coarse resolving time
Hit detector time
b
Accept window
end time
a
b
a<b
b
a
Trigger window
end time
a<b
b
J.P.Martin, ECFA_DESY
Workshop, Amsterdam, 1-4 April
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Details of the feature extraction (example)
Accept signal
FADC bits
Digital
triangular
filter
Digital
differentiator
Amplitude of filtered peak
Peak
detector
Above threshold
Negative
values suppressor
Centroid
evaluator
Linearisation
function
Time vernier
Pulse shape data
FADC data gate
Time stamp (clock counter)
J.P.Martin, ECFA_DESY
Workshop, Amsterdam, 1-4 April
5
QUARTUS II top level diagram of KOPIO digital filters
J.P.Martin, ECFA_DESY
Workshop, Amsterdam, 1-4 April
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KOPIO flat top digital filter, QUARTUS II diagram
J.P.Martin, ECFA_DESY
Workshop, Amsterdam, 1-4 April
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Preliminary specifications for a TCP readout application
•Analog inputs: 48 differential pairs, 100 ohms impedance, flat cable or
twisted pairs, 100 pin fine pitch (0.025”) connector
•Dynamic range: 1000:1
•Analog dynamic range of ADC: plus/minus 0.5 volts
•Analog gain before ADC: fixed between 2 and 20 according to
requirement, DC coupled
•Maximum pulse shape sampling frequency: 40 MHz
•Low pass filter cutoff frequency, <1/2 sampling frequency
•Timing resolution: <5 nanoseconds with 20:1 S/N ratio
•Trigger rate: limited by readout system throughput:
- For VME, reading out only the time and amplitudes, 20
modules in a crate, about 15 KHz;
full pulse shape readout, 960 channels, 100 samples: 10 Hz
with zero suppression: scales according to occupancy
-For LVDS, one to 20 times faster, according to the readout
of the LVDS data collector modules, assumong no processing
in the collector modules
J.P.Martin, ECFA_DESY
Workshop, Amsterdam, 1-4 April
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Picture of the PCB at the current stage of development
J.P.Martin, ECFA_DESY
Workshop, Amsterdam, 1-4 April
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Milestones
• Completion of the PCB routing: 30 April 2003
• Delivery of the PCB bare boards: 15 May 2003
• First prototype manually populated and electrically tested: 3 rd week of June 2003
• Prototype working with the minimal KOPIO firmware: mid July 2003
• Refinement of KOPIO firmware completed: mid August
• Modifications for other applications (i.e. TPC) : starting mid August
J.P.Martin, ECFA_DESY
Workshop, Amsterdam, 1-4 April
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