International ECFA/DESY Workshop Amsterdam, 1-4 April 2003 CMOS Monolithic Active Pixel Sensors for the Linear Collider. A Flexible Approach. P.
Download ReportTranscript International ECFA/DESY Workshop Amsterdam, 1-4 April 2003 CMOS Monolithic Active Pixel Sensors for the Linear Collider. A Flexible Approach. P.
International ECFA/DESY Workshop 1 Amsterdam, 1-4 April 2003 CMOS Monolithic Active Pixel Sensors for the Linear Collider. A Flexible Approach. P. Allport4, R. Bates2, G. Casse4, C. Castelli1, A. Evans4,5, C. Eyles1, M. French5, A. Holland3, H. Mapson1, Q. Morrissey5, V. O’Shea2, M. Prydderch5, R. Turchetta5, M. Tyndel5, J. Velthuis4, G. Villani5, N. Waltham5 1 University of Birmingham, 2 University of Glasgow, 3 University of Leicester, 4 University of Liverpool, 5 Rutherford Appleton Laboratory Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003 International ECFA/DESY Workshop 2 Amsterdam, 1-4 April 2003 Outline Introduction Science-grade CMOS sensors Technology choice Current status Concept How it works Design of a ladder for the Vertex detector Future developments Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003 International ECFA/DESY Workshop 3 Amsterdam, 1-4 April 2003 CMOS sensors design in RAL Goal: to design science-grade sensors. for Particle Physics, Space Science, … This requires: full-custom designed tailored to specific applications new designs Good imaging performances CMOS sensor technologies Many foundries propose three flavour of a given technology: digital, analogue and image sensors At present we are using a CMOS Image Sensors (CIS) 0.25 mm process low leakage current, low number of defects, good sensitivity to the whole spectrum of light (absorption length for red a few mm) thick epitaxial layer (8 mm) integration of colour filters, microlenses Up to 5 metal layers for complex routing Metal-to-metal capacitors for precise analogue design Dual power supply: 2.5/3.3 V. Good for low power consumption and good analogue performances Multiple choice of transistors Vt gives more flexibility to the designer Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003 4 Amsterdam, 1-4 April 2003 International ECFA/DESY Workshop RAL CMOS camera-on-chip Designed in standard CMOS 0.5 mm 512 by 512 array of 25mm pixels Camera-on-a-chip 10-bit ADC integrated (1 per column) with all the control logic Example of snapshot Simple, only digital PC-based DAQ Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003 International ECFA/DESY Workshop 4K linear device Science-grade sensors 256x384 test structure 3 mm pitch Flexible APS: this talk 1m-resolution Earth Observation 5 Amsterdam, 1-4 April 2003 in 0.25 mm CIS Design in 0.25 mm CMOS 200 mm diameter wafers. Image Sensor 4Kx3K = 12M pixels 5 mm pitch 4MOS pixel with CDS EUV Solar Orbiter 0.25 mm and 8” (200 mm) wafers 12 wafers manufactured. Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003 International ECFA/DESY Workshop 6 Amsterdam, 1-4 April 2003 Flexible APS (FAPS) for Linear Collider Standard New FAPS Memory #1 Select Memory #2 Reset Reset 1 A Out Select 1 Out The in-pixel amplifier accesses the ‘Out’ line, which is connected to all the pixels in a column relatively large capacitive load (>~ pF) relatively slow (1-10 Kfps) Memory #n The in-pixel amplifier accesses only local storage capacitors small capacitive load (<<pF) Write and read phase separate fast (>1 Mfps) Test structures with different designs and 5 FAPS arrays of 40*40*10 (time slices) pixels Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003 International ECFA/DESY Workshop 7 Amsterdam, 1-4 April 2003 Flexible Active Pixel Sensor (FAPS). The storage is user controlled and any time sequence can be programmed Simple snapshot (rolling shutter also possible) Time slices can have any time separation, from fraction of msec upwards The readout can be done in much the same way as a standard APS One sample can be used to store the reset value inpixel CDS possible Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003 International ECFA/DESY Workshop 8 Amsterdam, 1-4 April 2003 FAPS pixel layout Present design (proof-of-principle) 5 arrays with slightly different designs. Each array: 40*40 pixel Each pixel: 20 mm pitch and 10 storage cells Present number of memory cell is not a limit more memory cells possible Designed with 3 metal layers. Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003 International ECFA/DESY Workshop 9 Amsterdam, 1-4 April 2003 Timing Readout done as in a conventional APS Amplifier active only during writing in the capacitance reduced power consumption Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003 International ECFA/DESY Workshop Amsterdam, 1-4 April 2003 10 FAPS simulation result Single event: sampling spaced by 100ns and then readout at 1 MHz. Charge injected every 200 ns Analogue output Linearity: good linearity up to 30,000 electrons. It can accommodate for leakage current increases and/or large signals Current status. Test in preparation. Generic DAQ module designed. PC-based setup. Sampling control signals Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003 International ECFA/DESY Workshop 11 Amsterdam, 1-4 April 2003 Large-area sensor Option 1: clever dicing (some dead space). See 200 mm wafer in a 0.25 mm CMOS technology picture on the right. Cost-effective solution for prototyping. 12Mpixels Option 2: stitching (seamless) Plan: use the 4Kx3K sensor to gain experience on issues such as yield, uniformity, specific 36Mpixels design issues. Clever dicing build a 6Kx12K, i.e.72 M pixel sensor 72Mpixels Work, in collaboration with the CMOS foundries, for a stitched device Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003 12 Amsterdam, 1-4 April 2003 International ECFA/DESY Workshop CMOS sensors for the linear collider 50 mm 50 mm Readout direction 13 mm Red line: control electronics (sampling and readout). Minimal space. Guidelines Red rectangle: readout electronics (column amplifiers + ADC + sparsifying circuit) CCD talk Either on same substrate or bump-bonded to sensor substrate Ladder with 1 sensor Sensor size: 100 mm *13 mm, read out at both sides Number of pixels per sensor: 2500 x 650 In each pixel: 20 samples Minimize budget material in the central area Keep power dissipation evenly spread and low Keep sensor architecture simple and adaptable to machine choice Simplify system design For Tesla: sample at 50 ms during beam-on periods and store 20 samples in the pixel Column parallel readout between trains: 2500*20=5*104 samples at 5 MHz 10 ms For NLC/JLC: number of samples depending on readout speed. It would give reduced pixel occupancy. E.g.: readout at 5 MHz during 8 ms 16 samples: 2500*16=4*104 samples at 5 MHz 8 ms Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003 International ECFA/DESY Workshop Amsterdam, 1-4 April 2003 13 Conclusion / Summary UK collaboration to develop CMOS sensors for particle physics and space science RAL has proved capability in complex design of camera-on-a-chip sensors and is developing science-grade CMOS sensors for a broad range of applications. Flexible APS architecture suitable for Linear Collider Large area sensor 4k*3k 12 M pixels *6 72 M pixels sensor Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003 International ECFA/DESY Workshop 14 Amsterdam, 1-4 April 2003 Layer 2/3/4/5 sensor 22 mm 125 mm Readout direction Ladder with 2 sensors Sensor size: 125 mm * 22 mm, read out on one side Number of pixels per sensor: 6250 x 1100 For Tesla: sample at 250 ms during beam-on periods and store 4 samples in the pixel Column parallel readout between trains: 6250*4=2.5*104 samples at 5 MHz 5 ms. More samples possible For NLC/JLC: number of samples depending on readout speed if higher time segmentation is required. E.g.: readout at 5 MHz during 8 ms 16 samples: 6250*6=3.75*104 samples at 5 MHz 7.5 ms Instrumentation Department Microelectronics Design Group R. Turchetta 3 April 2003