Transcript DEPFET pixel sensor – concept and status R.H. Richtera, L. Andriceka, P.

DEPFET pixel sensor – concept and status
R.H. Richtera, L. Andriceka, P. Fischerb, G. Lutza, I. Pericc, J. Treisa, M. Trimplc, N. Wermesc
aMPI Halbleiterlabor Munich
bUniv. of Mannheim
cUniv. of Bonn
» DEP(leted)F(ield)E(ffect)T(ransistor) operation principles
» DEPFET prototype run
» Simulation and design examples
» Production status
» Read out electronics and steering chips
» Summary
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
DEPFET-Principle
Radiation
source
top gate
n+
p+
p-channel
internal gate
+
bulk
p+
n+
-n - +
-+
-+
-
drain
potential via axis
top-gate / rear contact
~1mm
~300 mm
totally depleted
n--substrate
potential minimum
for electrons
p+
rear contact
V
FET integrated on high ohmic n-bulk
Advantages:
of thethe
charge
at the
position of collection
Collection Amplification
of electrons within
internal
gate
=> no transfer loss
ModulationFull
of the
FET
current by the signal charge!
bulk
sensitivity
Non structured thin entrance window (backside)
Very low input capacitance => very low noise
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Proposed concept for TESLA
readout chips
matrix is read out
row-wise
520 x 4000 pixel
DEPFET-Matrix
(25 x 25 µm pixel)
steering chips
• thin detector-area
readout chips
first thinned samples:
down to 50µm
• frame for mechanical
stability carries readoutand steering-chips
[L.Andricek, MPI Munich]
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Excellent noise values measured on single pixels
Ka
6000
5000
# Zähler
4000
3000
2000
Escape - Peak
Kb
1000
0
2
4
6
Energie [keV]
55Fe-spectra
@ 300K
ENC = 4.8 +/- 0.1 eR. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
BioScope - imaging of tracer-marked bio-medical samples
(P. Klein and W. Neeser)
Noise: ca. 70 ENC @ 300K
Slow operation (old technology)
Large arrays are impossible
(JFET => VP variations)
Large cell size
DEPFET pixel matrix
Low power consumption
Fast random access to
specific array regions
- Read filled cells of a row
- Clear the internal gates
of the row
- Read empty cells
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
DEPFET Technology
on 6” wafer
Double poly / double aluminum process
on high ohmic n- substrate
along p-channel
perpendicular to channel (with clear)
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Rectangular DEPFET pixel detector
MOS transistor instead of JFET
A pixel size of ca. 20 x 20 µm² is
achievable using 3µm minimum
feature size.
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Active Pixel Sensor (rectangular)
•
2 pixels
30 x 30 µm²
•
DEPFET
L = 5 µm
W = 18 µm
 reduce the required read out
speed by 2
doubles the number of read out
channels
Potential during collection - 3D Poisson equation (Poseidon)
(50µm thick Si, NB=1013cm-3,VBack=-20V)
Depth 10µm
Depth
Depth1µm
4µm
7µm
External (internal) Gates
Drain
n+ clear contacts
Sources
Cell size 36 x 27 µm²
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Current production status
Pixel array section – design with clockable clear gate
1 pixel cell
Drain
Gate
Done:
N-side with two polysilicon layers and
contact openings
Backside processing
Aluminium Sputtering
To do:
- 1st metal lithography (2 weeks)
- First measurements
- 2nd metal process
Clear
Clear
gate
Source
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Readout architecture (triggerless)
DEPFET provides current + fast readout needed
current based readout (see Vertex2002 proceedings)

keep potential at input node constant
(regulated cascode)
 (signal+pedestal current) stored in current
memory cell (inverting property)
 pedestal current after reset subtracted
automatically

signal value is stored in FIFO (analog part)

FIFO is emptied row wise:

hit identification with current comparator and
store hit pattern in FIFO (digital part)
• ‘hit finder’ identifies hits in a row
and multiplexes (MUX) the appropriated currents to ADC
(respective analogous outputs)
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Chip development for TESLA
Readout chip 1.0:
 TSMC 0.25µm, 5metal
 radiation tolerant
design with annular
nmos transistors
 contains: various
current memory cells,
hit finder,
comparator
 size: 4 x 1.5 mm2
Steering chip:
[I.Peric (Bonn) / P.Fischer (Mannheim)]
 AMS 0.8µm HV-Process
 steers 64 DEPFET-rows (cascadable)
 size: 4.6 x 4.8 mm2
 internal sequencer  flexible pattern
[M.Trimpl (Bonn)]
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Results
steering chip:
works with 50MHz @ 15pF load capacitance
I2U
R/O chip:
digital part:
hitfinder und comparator work with 50MHz
 Readout concept works
[Testsetup for current memory cells]
350
Samplenoise of memory cell
300
noise [electrons]
analoge performance:
• 25 MHz sample frequency
• 0.1 % differential nonlinearity
(for 10µA (~ 10000 e-) dyn. input range)
• 38 e- Noise (for complete analogous stage)
U2I
250
-
200
m = 27,74 +/- 0,44 e / sample
c = 15,82 +/- 3,6 e
150
100
@ room-temperature
25 MHz - Samplefrequency
50
2
4
6
sqrt (samples)
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
8
10
12
Prototype system ...
R/O chip (July 2003):
DEPFET -Matrix
(25x25 µm)
Reset-Switcher
Gate-Switcher
Hybrid
• readout chip with 128 channels
• 50MHz sample frequency
• 25 e- noise
Hybrid-PCB with
• separate steering chips für select und reset
• 64x128 pixel array
• new R/O-Chip
R/O Chip 2.0
Readout-PCB
Sequencer
ADC
Readout-PCB with
• ADC and RAM (external)
• Datatransfer between Hybrid and PC
DATA-RAM
Controller
PC
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Summary / schedule
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Key features: low noise, full bulk sensitivity, no charge transfer loss, low power
consumption, random access within an array
A new DEPFET technology (2 poly/ 2 aluminum) was developed for large arrays and
high speed operation.
A DEPFET prototype production has been started with DEPFET arrays
30 x 30 µm² pixel size.
First measurements in 2 weeks
Read out electronics first test chip successfully tested (50MHz operation possible)
128 channel read out chip (2.0) currently in design, submission this month, chip
delivery in summer
Steering chip for Gate and Clear access successfully fabricated
(first tests very encouraging)
Complete prototype system ready by end of the year
Further plans
In 2004: Design and production of large arrays
Some wafer on SOI (thinned technology) ?
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Back up transparencies
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Crossing polysilicon lines
Problems with demolished polysilicon lines
and bad polyI/polyII insulation
Solved now
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Self aligning Technology
Positions of all essential implantations
are determined not by masks
but by polysilicon layers
shallow channel implantation
- mandatory for rectangular cells
(lateral channel definition)
- reduces parameter variations
on the wafer
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Hiding the n+-clear contacts
Depth 1µm
The positive Clear pulse removes the electrons
from the Internal Gate and also pushs the holes
out of the deep p cover region. After returning of the
clear the deep p remains negatively charges forming
a shield for the signal electrons.
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
Simulation of the Clear mechanism
TeSCA (2D, time dependent)
Removal of 1600 electrons from the
internal gate (VClear=15V)
Poseidon (3D Poisson equ.)
Includes 3D effects =>
VClear=20V
Pixel prototype production (6“ wafer)
for XEUS and LC (TESLA)
Aim: Select design options for an optimized array operation
(no charge loss, high gain, low noise, good clear operation)
On base of these results => production of full size sensors
Many test arrays
- Circular and linear DEPFETS
up to 128 x 128 pixels
minimum pixel size about 30 x 30 µm²
- variety of special test structures
Production will be finished in spring
R. H. Richter et al - ECFA/DESY Linear Collider Workshop, Amsterdam, 1 - 4 April 2003
imaging spectroscopy
purpose
particle tracking
7.68 x 7.68 cm²
1024 x 1024 pixels
detector format
1.3 x 10 cm² (x 8)
520 x 4000 pixels (x 8)
1 Mpix
2.1 Mpix (x8)
75 µm
pixel size
25 µm
300 ... 500 µm
thickness
50 µm
4 el. ENC
noise
~ 100 el. ENC
1.2 msec
2.5 µsec
readout time
/ detector
/ row
50 µsec
20 nsec