Transcript 2010 Materials Research Society Spring Meeting, April 7, San Francisco A Self-Aligned Epitaxial Regrowth Process for Sub-100-nm III-V FETs Mark.

2010 Materials Research Society Spring Meeting, April 7, San Francisco
A Self-Aligned Epitaxial Regrowth Process
for Sub-100-nm III-V FETs
Mark. Rodwell,
University of California, Santa Barbara
A. D. Carter, G. J. Burek, M. A. Wistey*, B. J. Thibeault, A. Baraskar, U. Singisetti,
J. Cagnon, S. Stemmer, A. C. Gossard, C. Palmstrøm
University of California, Santa Barbara
*Now at Notre Dame
B. Shin, E. Kim, P. C. McIntyre
Stanford University
Y.-J. Lee
Intel
B. Yue, L. Wang, P. Asbeck, Y. Taur
University of California, San Diego
III-V MOS: What is needed ?
True MOS device structures at ~10 nm gate lengths
10nm gate length, < 10nm electrode spacings, < 10nm contact widths
< 3 nm channel, < 1 nm gate-channel separation, < 3nm deep junctions
Fully self-aligned processes: N+ S/D, S/D contacts
Drive currents >> 1 mA/micron @ 1/2-Volt Vdd.
Low access resistances.
Density-of-states limits.
Dielectrics: < 0.6 nm EOT , Dit < 1012 /cm2-eV
impacts Ion, Ioff , ...
Low dielectric Dit must survive FET process.
...and the channel must be grown on Silicon
FETs
FET Scaling Laws
LG
Changes required to double device / circuit bandwidth.
laws in constant-voltage limit:
FET parameter
gate length
current density (mA/mm), gm (mS/mm)
channel 2DEG electron density
electron mass in transport direction
gate-channel capacitance density
dielectric equivalent thickness
channel thickness
channel density of states
source & drain contact resistivities
Current densities should double
Charge densities must double
change
decrease 2:1
increase 2:1
increase 2:1
constant
increase 2:1
decrease 2:1
decrease 2:1
increase 2:1
decrease 4:1
gate width WG 
Semiconductor Capacitances Must Also Scale
(Vgs  Vth )
( unidirecti onal motion)
cox
cdepth   / Tinversion
( E f  Ewell ) / q
cdos  q 2 gm* / 2 2
channel charge  qns  cdos (V f  Vwell )  q( E f  Ewell )  ( gm* / 22 )
Inversion thickness & density of states must also both scale.
Calculating Current: Ballistic Limit
Channel Fermi voltage  voltage applied to cdos
determines Fermi velocity v f through E f  qV f  m * v 2f / 2
mean electron velocity  v  ( 4 / 3 )v f
Channel charge : s  cdos
V
f
V  
c
cdoscequiv
cequiv  cdos
V
gs
 Vth 
cdos  q2 gm * / 22  cdos,o  g  (m * / mo ) , where g is the # of band minima
 mA 
 Vgs  Vth 
g  (m * / mo )1 / 2
 J   84


3/ 2 

m
m
1
V



 1  (cdos,o / cox )  g  (m * / mo ) 

3/ 2
Do we get highest current with high or low mass ?
Drive Current Versus Mass, # Valleys, and EOT
 mA   Vgs  Vth 
J  K   84
  

m
m
1
V

 

0.35
3/ 2
g  m* mo 
1/ 2
, where K 
InGaAs <--> InP
1  (c
*
dos,o / cequiv )  g  ( m / mo ) 
3/ 2
Si
g=2
g=1
0.3
cequiv  ( 1/cox  1/cdepth )1
0.25
 εSiO2 /EOT
0.2
K
0.3 nm
0.15
0.4 nm
0.1
0.6 nm
0.05
EOT includes the wavefunction depth term
(mean wavefunction depth*SiO2 /semiconductor )
0
0.01
0.1
m*/m
EOT=1.0 nm
1
o
Standard InGaAs MOSFETs have superior Id to Si at large EOT.
Standard InGaAs MOSFETs have inferior Id to Si at small EOT.
Transit Delay versus Effective Mass
1/ 2
Lg
 m*

  1 Volt 


 ch  K 2  

where
K


2
7



 2.52  10 cm/s   Vgs  Vth 
 m0 
1/ 2
EOT=1.0 nm
1.5
1/ 2
 cdos,o

m
*

 1 
g

ceq
mo 

0.6 nm
normalized transit delay K
2
1 nm
0.4 nm
0.6 nm
0.4 nm
1
cequiv  ( 1/cox  1/cdepth )1
 εSiO2 /EOT
g=1, isotropic bands
0.5
g=2, isotropic bands
EOT includes wavefunction depth term
(mean wavefunction depth*SiO2 /semiconductor )
0
0
0.05
0.1
0.15
0.2
0.25
m*/m
0.3
0.35
o
Low m* gives lowest transit time, lowest Cgs at any EOT.
0.4
III-V MOSFETs for VLSI: Why and Why Not.
Lower mass → Higher Carrier Velocity→ lower input capacitance
improved gate delay in transistor-capacitance-limited gates
not relevant in wiring-capacitance-limited gates (i.e. most of VLSI)
More importantly: potential for higher drive current
improved gate delay in wiring-capacitance-limited gates (VLSI)
But this advantage is widely misunderstood in community
InGaAs channels→ higher Id / Wg than Si only for thick dielectrics
....LOWER Id / Wg than Si for thin dielectrics
break-even point is at ~0.5 nm EOT
We will introduce (DRC2010) candidate III-V channel designs
providing higher Id / Wg than Si even for small EOT
Contacts: Low Resistivity, High Current Density
sidewall
gate dielectric
metal gate
source contact
N+ source
drain contact
quantum well / channel
N+ drain
barrier
substrate
For  10% impact on drive current,
I D RS /(VDD  Vth )  0.1
Target I D / Wg ~ 1.5 mA/ mm @ (VDD  Vth )  0.3 V
 RsWg  20   mm
10 nm wide contact   c  0.2   mm2 (! )
current density in contact  150 mA/ mm2  refractory contacts
FET: Key Regions, Key Challenges
For each 2:1 reduction in gate length:
contacts:
4:1 reduction in
contact resistivity
2:1 shallower
4:1 higher J
gate dielectric:
2:1 reduction in thickness
limit: tunneling→high-K
limit (high-K): defects
channel :
2:1 increase in electron density @ same voltage
limit: # available electron states / area / energy
"density of states bottleneck"; perceived to be fundamental
Highly Scaled FET
Process Flows
Scalable nm III-V MOSFET: what is needed
True MOS device structures at ~10 nm gate lengths
10 nm gate length, < 10nm electrode spacings, < 10nm contact widths
< 3 nm channel, < 1 nm gate-channel separation, < w nm deep junctions
Fully self-aligned processes: N+ S/D, S/D contacts
InGaAs MOSFET with N+ Source/Drain by MEE Regrowth1
HAADF-STEM1*
InGaAs
regrowth
Interface
InGaAs
2 nm
* TEM by J. Cagnon, Susanne Stemmer Group, UCSB
Self-aligned source/drain defined by MBE regrowth2
Self-aligned in-situ Mo contacts3
Process flow & dimensions selected for 10-30 nm Lg design;
1Singisetti,
2Wistey,
ISCS 2008
EMC 2008
3Baraskar,
EMC 2009
Regrown S/D process: key features
Self-aligned & low resistivity
...source / drain N+ regions
...source / drain metal contacts
Vertical S/D doping profile set by MBE
no n+ junction extension below channel
abrupt on few-nm scale
Gate-first
gate dielectric formed after MBE growth
uncontaminated / undamaged surface
Process flow*
* Singisetti et al, 2008 ISCS, September, Frieburg
Singisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009
Key challenge in S/D process: gate stack etch
Requirement: avoid damaging semiconductor surface:
Approach: Gate stack with multiple selective etches*
FIB Cross-section
SiO2
Damage free channel
Cr
W
Process scalable to ~10 nm gate lengths
* Singisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009
Challenge in S/D process: dielectric sidewall
-3
electron concentration (cm )
sidewall
19
2.8 10
source
gate
19
2.4 10
2 10
19
19
1.6 10
19
1.2 10
8 10
18
4 10
18
10nm SiN
20 nm SiN
30 nm SiN
0
10
20
30
40
50
distance (nm)
ns under sidewall:
electrostatic spillover from source, gate
Sidewall must be kept thin:
avoid carrier depletion,
avoid source starvation
60
70
spillover
80
MBE Regrowth→ Gap Near Gate→ Source Resistance
Ti/Au Pad
SiO2 cap
SEM
Mo+InGaAs
W / Cr /
SiO2
W/Cr
gate
gate
Gap in regrowth
SEM
/ Cr / SiO
• Shadowing by gate: No regrowth nextWto
gate
2
gate
• Gap region is depleted of electrons
High source resistance because of electron depletion in the gap
MBE growth by Dr. Mark Wistey, device fabrication and characterization by U. Singisetti
Migration Enhanced Epitaxial (MEE) S/D Regrowth*
High T migration enhanced
45o tilt SEM
Epitaxial (MEE) regrowth*
No Gap
gate
Top of SiO2 gate
Side of gate
regrowth interface
No Gap
High temperature migration enhanced epitaxial regrowth
*Wistey, EMC 2008
Wistey, ICMBE 2008
MBE growth by Dr. Mark Wistey, device fabrication and characterization by U. Singisetti
Regrown S/D III-V MOSFET: Images
SiO2
SiNx
Cr
W
InGaAs
regrowth
W/Cr gate Pad
Original
interface
Cross-section after regrowth,
but before Mo deposition
Mo
+InGaAs
Ti/Au Pad
Top view of completed device
Source Resistance: electron depletion near gate
SiO2
SiNx
InGaAs
regrowth
Cr
W
R1
R2
• Electron depletion in regrowth shadow region (R1 )
• Electron depletion in the channel under SiNx sidewalls (R2 )
Original
interface
Regrowth profile dependence on As flux*
SiO2
InAlAs
InGaAs
InGaAs
Cr
increasing As flux
InGaAs
W
InGaAs
regrowth
surface
uniform filling
multiple InGaAs regrowths with InAlAs marker layers
Uniform filling with lower As flux
* Wistey et al, EMC 2009
Wistey et al NAMBE 2009
MBE growth by Dr. Mark Wistey, device fabrication and characterization by U. Singisetti
InAs source/drain regrowth
Gate
InAs
regrowth
top of gate
side of gate
Mo S/D metal with
N+ InAs underneath
Improved InAs regrowth with low As flux for uniform filling1
InAs less susceptible to electron depletion: Fermi pinning above Ec2
1
Wistey et al, EMC 2009
Wistey et al NAMBE 2009.
2Bhargava
et al , APL 1997
In-Situ Refractory Ohmics on MBE Regrown N-InGaAs
5
8
In-situ Mo on n-InAs
3
2
ρc = 0.6 ± 0.4 Ω·µm2
1
Resistance ()
Resistance ()
4
In-situ Mo on n-InGaAs
6
4
ρc = 1.0 ± 0.6 Ω·µm2
2
n = 5×1019 cm-3
n = 1×1020 cm-3
0
0
0.5
1
1.5
2
2.5
Gap Spacing (mm)
3
3.5
00
0.5
1
1.5
2
2.5
3
3.5
Gap Spacing (mm)
HAADF-STEM*
InGaAs
regrowth
Interface
InGaAs
2 nm
TEM by Dr. J. Cagnon, Stemmer Group, UCSB
A. Baraskar
Benefits of refractory contacts
15 nm Pd/Ti diffusion
100 nm InGaAs grown in MBE
30 nm Mo
After 250°C anneal, Pd/Ti/Pd/Au diffuses 15nm into semiconductor
deposited Pd thickness: 2.5nm
Refractory Mo contacts do not diffuse measurably
Refractory, non-diffusive metal contacts for thin semiconductor layers
A.. Baraskar
Resistivity of MEE Regrowth
Voltage (mV)
15 mm TLM width
~50 nm InAs regrowth has ~22  sheet resistivity
Contact resistivity is ~1.2 -mm2.
Self-Aligned Contacts: Height Selective Etching*
Mo
PR
PR
PR
InGaAs
Dummy gate
No regrowth
* Burek et al, J. Cryst. Growth 2009
Fully Self-Aligned III-V MOSFET Process
D
drain current, I (mA/mm)
0.8
L = 200 nm W = 8 mm
0.7
g
g
V : 0 to 4 V in 0.5 V steps
0.6
gs
0.5
0.4
0.3
0.2
0.1
0
0
0.2
0.4
0.6
V
DS
(V)
0.8
1
Subthreshold characteristics
10
-2
L =1.0 mm
L =0.35 mm
10
-3
10
-4
10
-5
g
325 mV/decade
d
I (A)
g
10
-6
10
-7
10
290 mV/decade
V =0.1V
V =0.1V
V =1.0V
V =1.0 V
ds
ds
-8
ds
ds
10
-9
-1
0
1
2 3
V (V)
gs
4
5
-1
0
1
2 3
V (V)
gs
4
5
10-30 nm Process Development
SiO2 +
SiNx
Field: SiNx
Cr +
SiNx
W+
SiNx
Excellent structural yield in
sub-100nm process flow
27 nm Self-Aligned InGaAs MOSFET
Self-aligned N+ S/D regrowth
shallow , high doping , low sheet 
Self-aligned Mo in-situ S/D contacts:
low  , refractory → shallow
HAADF TEM
HAADF TEM
STEM is chemical contrast imaging -> Is the regrowth sinking?
Conclusion
III-V MOS
With appropriate design, III-V channels can provide > current than Si
...even for highly scaled devices
But present III-V device structures are also unsuitable for 10 nm MOS
large access regions, low current densities, deep junctions
Raised S/D regrowth process is a path towards a nm VLSI III-V device
(end)