Transcript Local Video System: Overview EECS150 Fall 2008 - Lab Lecture #7 Ke Xu 11/6/2015 EECS150 Lab Lecture #8

Local Video System: Overview
EECS150 Fall 2008 - Lab Lecture #7
Ke Xu
11/6/2015
EECS150 Lab Lecture #8
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Welcome to Checkpoint 1
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First real design checkpoint
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Video in SDRAM
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No datasheets!
Motivation
Storage
FIFO Controllers
SDRAM Arbiter
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The Big Idea(1)
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The Big Idea(2)
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Combining checkpoint 1 (SDRAM) + two
video modules
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We’ll give you the video decoder + video encoder
Video Decoder writes a frame into SDRAM
Video Encoder reads the frame from SDRAM
Arbiter sits between SDRAM Controller and
Decoder/Encoder to make sure the SDRAM
Controller sees only one request at a time
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Video Encoder
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Previous semesters had to implement
this as a checkpoint.
This semester, the Video Encoder
module will be black-boxed.
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Saves the class from having an excessive
number of checkpoints.
Will be replaced by the last checkpoint,
which is video compression (DCT +
Huffman).
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Short Video Summary
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ITU-R BT.601
ITU-R BT.656
Luma/Chroma Y CR Y CB Pixel Pairs
Vertical/Horizontal Active/Blanking
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Video References
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Past Lab Lecture on video encoder
posted online.
Sample design document (Chen’s)
already posted on the website.
Check documentation (ADV7194 Video
Encoder, ADV7185 Video Decoder) on
website.
Past checkpoint pdf spec also posted
online.
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Checkpoint 2
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Part I: Encode/Decode FIFO Controllers
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Part II: Arbiter
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Address Counters determine read/write addresses
FSM determines when to request read/write
Need to handle simultaneous requests.
Handles writes from decode processor
Handles reads from encode processor
Ensures that one request is given to SDRAM
Controller at a time
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FIFO Controllers (1)
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Decoder FIFO Controller
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Store active video data from decoder into FIFO
Write to SDRAM when FIFO has enough data
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Assert a write request when FIFO has at least 8 words
Ensures that FIFO does not underflow
Controls the write address counter
Similar to encoder FIFO controller
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Dual Clocked FIFO
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The FIFO on the decoder side uses two
independent clocks: one for reading,
one for writing.
The camera runs on its own 27MHz
clock.
You can use ModelSim to figure out
how to interpret each of the control
signals.
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FIFO Controllers (2)
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Encoder FIFO Controller
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Reads active video data from SDRAM
Reads from SDRAM when FIFO has enough
space
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Assert a read request when FIFO is less than ¾
full
Must ensure that FIFO never overflows
Controls the read address counter
Sends data from FIFO to VideoEncoder
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More on FIFOs
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Why a FIFO?
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Data Rate Matching
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Buffering
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SDRAM handles data at 32 bits per cycle
Encoder handles data at 32 bits per 4 cycles
Encoder needs a continuous stream of data
SDRAM might be busy
The FIFO “Predicts” what data the video
encoder will want and supplies it upon request
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Announcements
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Checkpoint 1
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Please make sure to finish your checkpoints
on time.
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Checkpoint 1 due next week in your respective lab
sections.
Demonstrate working implementation of your
checkpoint.
Knowledge of SDRAM Controller timing is essential
for checkpoint 2
Once you finish one checkpoint, your attention will
then immediately focus on the next checkpoint.
Lateness means you will only fall further behind.
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SDRAM Arbiter (1)
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Essentially, you’re replacing Checkpoint0bb
with your own useful implementation.
Controls interface with SDRAM Controller
Sets priority between Decoder and Encoder
SDRAM Controller thinks there is only 1 port
SDRAM Arbiter allows multiple access ports
Funnels control signals selectively to each
port
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SDRAM Arbiter (2)
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You will need to add more states to this
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Arbiter Handshaking Protocol
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Once the SDRAM Controller has finished initializing, the arbiter
will start polling the decoder and encoder for requests
(simultaneously).
If both modules are ready, the arbiter should give priority to the
encoder.
If neither module is ready, the arbiter should poll again.
If either module is ready, the arbiter must appropriately assert
read/write requests to the SDRAM controller, and control signals
to the FIFO controllers
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YOU MUST REVIEW THE TIMING FOR HANDLING
REQUESTS IN YOUR SDRAM CONTROLLER.
THE CONTROL SIGNALS MUST BE TIMED PERFECTLY OR
YOUR PROJECT WILL NOT WORK
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How is the video data stored?
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Modifications Needed for CP0
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Recall from Checkpoint 0:
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In this checkpoint:
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RAM Address = {Row, Bank, Column}
RowAddress = {4’h0, PixelRow, Field}
BankAddress = 2'h0
ColumnAddress = {BurstColumn, 3'h0}
You will modify your address counter to
accommodate exactly the right amount
of active video data.
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Video Again
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ITU 601 Standard
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The video camera follows the ITU 601
standard, which has 507 active lines.
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Odd Field (262 Lines)
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Even Field (263 Lines)
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6 Vertical Blanking, 254 Active, 2 Vertical Blanking
7 Vertical Blanking, 253 Active, 3 Vertical Blanking
The provided video decoder sends video
data order {Cb, Y, Cr, Y}.
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Tips, Hints, & Common Pitfalls
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Timing for writing is tricky. Recall from
Checkpoint 1 that the black box puts
data on the DQ line based only on
WriteRequest timing. You’ll have to
take care of this timing yourself now.
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Tips, Hints, & Common Pitfalls
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Make your arbiter design very clean
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The lab specification states that most
modules can be implemented in ¾ states.
You’ll need to extend your arbiter to
accommodate four ports for Checkpoint 4.
Your encode and decode processors
should be almost identical. They are
basically the same module.
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Tips, Hints, & Common Pitfalls
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Long synthesis
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Due to increased complexity of this checkpoint,
putting your design on the board can take up to
10 minutes.
Avoid the vicious cycle of:
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Changing one line
Generating the programming file
Fail
Repeat
If you catch yourself doing this, make ModelSim
testbenches. Yes, you can simulate the blackbox
FIFOs.
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Questions?
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