Transcript Verilog Synthesis & FSMs EECS150 Spring 2007 – Lab Lecture #3 Brent Mochizuki Greg Gibeling 2/2/07 EECS150 Lab Lecture #3

Verilog Synthesis & FSMs
EECS150 Spring 2007 – Lab Lecture #3
Brent Mochizuki
Greg Gibeling
2/2/07
EECS150 Lab Lecture #3
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Today
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Designing Digital Logic
Efficient Hardware Design
HDL Simulation
Blocking vs. Non-Blocking
Administrative Info
Lab #3: The Combo Lock
FSMs in Verilog
EECS150 Lab Lecture #3
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Designing Digital Logic (1)
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High Level Design
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Implementing the Design
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Top-Down Design
Different from testing!
Follow the flow of data
Start with Inputs
Determine State
Generate Outputs
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Designing Digital Logic (2)
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Start with Inputs
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What are they?
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Process Them
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Possible Values and Don’t Cares
Timing
Raw inputs are often not what you need
Might need delay/timing change
Might look for a specific value/range
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Designing Digital Logic (3)
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Determine State
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What does the module need to remember?
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Design Memory for State
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Has it seen a particular input?
How many cycles have passed?
Generalized FSM
Standard D Register
Counter
Shift Register
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Designing Digital Logic (4)
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Generate Outputs
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What are they?
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Possible Values
Timing
Create the outputs
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Don’t set them, they’re not variables
Compute them from state (and inputs)
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Learn to think in Boolean equations
assign is helpful
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Efficient Hardware Design (1)
B
always @ (*) begin
if (a) Z = A + B;
else Z =
A + C;
end
A
C
11
0
a
Z
always @ (*) begin
if (a) aux =B;
else aux = C;
Z =
A + aux;
end
B
C
1
0
A
a
aux
Z
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Efficient Hardware Design (2)
A
B
assign B = 3;
assign Z = A * B;
Z
A
assign Z = A + (2 * A);
<<
assign Z = A + (A << 1);
assign Z = A + {A, 1’b0};
n+1 bit adder
Z
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Efficient Hardware Design (3)
assign aux = A + {1’b0, A[n-1:1]};
assign Z = {aux, A[0]};
A[n-1:1]
A
A[0]
n bit adder
aux
Z
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HDL Simulation (1)
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Software Based Simulation
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Drawbacks
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Fast, simple and accurate
Allows for simulation at any precision
Easy to see any signal - perfect Visibility
Simulator Dependant
Deadlocks are Possible!
Simulation != Synthesis
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HDL Simulation (2)
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Implications
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Verilog is not executed!
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Things don’t necessarily happen in order
Verilog is SIMULATED
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Blocking vs. Non-Blocking (1)
Verilog Fragment
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Result
always @ (a) begin
b = a;
c = b;
end
C=B=A
always @ (posedge Clock) begin
b <= a;
c <= b;
end
B=A
C = Old B
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Blocking vs. Non-Blocking (2)
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Use Non-Blocking for FlipFlop Inference
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posedge/negedge require Non-Blocking
Else simulation and synthesis wont match
Use #1 to show causality
always @ (posedge Clock) begin
b <= #1 a;
c <= #1 b;
end
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Administrative Info
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Don’t expect to be checked off during
any lab times other than your own
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You should get checked off during your lab
or during your lab TA’s office hours
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Administrative Info (2)
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Partners - 1 week warning
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You MUST have one for Lab4 and later…
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If you do not have a partner:
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Try to keep the same one for the project
You must have one in your lab section
Find one now!!
Post to the newsgroup
E-mail Jeff
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Lab #3: The Combo Lock (1)
DIPSwitches
Code[1] Code[0]
1
0
1
0
Your Verilog
Lab4Compare
Open
ResetCombo
Reset
Lab4Top
(Lab4Lock)
Enter
Prog1
Prog2
Buttons
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Error
Outputs
Used to control entry to a locked room
2bit, 2 digit combo (By Default 11, 01)
Set code to 11, Press Enter
Set code to 01, Press Enter
Lock Opens (Open = 1)
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Lab #3: The Combo Lock (2)
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Signal
Width
Dir
Description
Code
2
I
Code from the dipswitches
Enter
1
I
Enter button (examine the code)
ResetCombo
1
I
Reset to the default combination
Clock
1
I
System Clock
Reset
1
I
System Reset, doesn’t affect the combo
Open
1
O
Indicates the lock is open
Error
1
O
Indicates a bad combination
Prog1
1
O
Reprogramming the first digit
Prog2
1
O
Reprogramming the second digit
LED
8
O
Use these for debugging
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Lab #3: The Combo Lock (3)
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Example 1:
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2:
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Press ResetCombo, Combo: 2’b11, 2’b01
Set 2’b11, Press Enter
Set 2’b01, Press Enter, LEDs: “OPEN”
Press Enter, LEDs: “Prog1”
Set 2’b00, Press Enter, LEDs: “Prog2”
Set 2’b10, Press Enter, LEDs: “OPEN”
Combo: 2’b00, 2’b10
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Lab #3: The Combo Lock (4)
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Example 2:
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1: Press ResetCombo, Combo: 2’b11, 2’b01
2: Set 2’b01, Press Enter
3: Set 2’b01, Press Enter, LEDs: “Error”
Why doesn’t “Error” show until step 3?
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Lab #3: The Combo Lock (5)
Code1 &
Enter
Init
~Code1 &
Enter
OK1
BAD1
Code2 &
Enter
~Code2 &
Enter
OK2
Enter
BAD2
Enter
[Open]
[Error]
Enter
Prog1
[Prog1]
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Enter
Prog2
[Prog2]
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Lab #3: The Combo Lock (6)
Code
0
1
0
Prog1/Prog2
1
Enter
Code[1] Code[0]
DIPSwitches
Code
2b
Code1Reg
2b
Reset
Combo
ResetCombo
Enter
Code2Reg
2b 2b
2b
==
==
2b
Lab4Compare
Enter
2b
Decode1
Decode2
Reset
Decode1
Decode2
Code1 &
Enter
Init
~Code1 &
Enter
Lab4Top
OK1
Prog1
Prog2
BAD1
Code2 &
Enter
~Code2 &
Enter
Enter
Enter
OK2
[Open]
BAD2
[Error]
Error
Prog1
Prog2
Outputs
Enter
Prog1
[Prog1]
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Open
Lab4Lock
Enter
Enter
EECS150 Lab Lecture #3
Prog2
[Prog2]
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Lab #3: The Combo Lock (7)
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Debugging with LEDs
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A powerful way to debug
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Easy to understand
Lower overhead than other debugging tools
A great way to see NextState/CurrentState
Drawbacks
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Slow, can’t see fast events
No timing information, no waveform
Limited number
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Dipswitches!
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FSMs in Verilog (1)
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Mealy Machines
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Output based on input
and current state
Can have major timing
problems
Moore Machines
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Mealy Machine
Output based on current
state
Easier to work with
Slightly harder to build
Moore Machine
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FSMs in Verilog (2)
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Two or Three always blocks
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1st: CurrentState Register
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2nd: Generates NextState (+ Outputs in Mealy)
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Uses CurrentState and Inputs
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Combinational
3rd: Generates Outputs (Optional)
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Clocked
Handles Reset
Uses CurrentState only (for Moore Machines)
Might be replaced with a few assigns
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FSMs in Verilog (3)
module MyFSM(In, Out, Clock, Reset);
input
In, Clock, Reset;
output
Out;
parameter
STATE_Idle =
STATE_Run =
STATE_X =
1’b0,
1’b1,
1’bx;
reg
CurrentState, NextState, Out;
always @ (posedge Clock) begin
if (Reset) CurrentState <= STATE_Idle;
else CurrentState <=
NextState;
end
…
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FSMs in Verilog (4)
…
always @ (CurrentState or In) begin
NextState = CurrentState;
Out =
1’b0;
// The case block goes here
// Its on the next slide…
end
endmodule
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FSMs in Verilog (5)
case (CurrentState)
STATE_Idle: begin
if (In) NextState = STATE_Run;
Out =
1’b0;
end
STATE_Run: begin
if (In) NextState = STATE_Idle;
Out =
1’b1;
end
default: begin
NextState =
STATE_X;
Out =
1’bX;
end
endcase
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