Transcript Digital Video and User Interface EECS150 Fall 2007 – Lab Lecture #7 Allen Lee Greg Gibeling 10/12/2007 EECS150 Lab Lecture #7

Digital Video and User Interface
EECS150 Fall 2007 – Lab Lecture #7
Allen Lee
Greg Gibeling
10/12/2007
EECS150 Lab Lecture #7
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Today
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10/12/2007
Checkpoint 1 Comments
Digital Video
Administrative Info
ITU-R BT.601
ITU-R BT.656
Video Encoder
I2C Bus
Video Display Module
EECS150 Lab Lecture #7
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Checkpoint 1 Comments (1)
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You need to implement the audio buffer
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You need to change the audio sampling and
output rate to 4kHz
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This is needed for record and playback
Don’t be afraid to modify FPGA_TOP!
Default is 48kHz. At this rate, the FIFO we gave
you can hold less than a second of data.
You need to set the VRA register before you can
change the audio rate (see p. 24 of datasheet).
EECS150 Lab Lecture #7
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Checkpoint 1 Comments (2)
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There’s been a minor update to the
documentation
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A solution bit file is under way
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10/12/2007
We removed some obsolete information
regarding the origin of PCM_DIn.
This does not affect the checkpoint.
Useful for testing that your mic works.
EECS150 Lab Lecture #7
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Digital Video (1)
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Pixel Array
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A digital image is
represented by a
matrix of pixels
which include color
information.
0
64
0
80
52 280
1
11
20
19
SIF,
82 Kpx
Frames
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2
35
0
24
Motion is created by
flashing a series of
still frames
Video, 300 Kpx
0
48
0
60
PC/Mac, 1 ‡2 Mpx
High-Definition Television (HDTV), 1 Mpx
0
72
Workstation, 1 Mpx
0
90
High-Definition Television (HDTV), 2 Mpx
80
10
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EECS150 Lab Lecture #7
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Digital Video (2)
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Scanning
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Images are generated on the screen by scanning pixel lines, left to right, top to
bottom
Early CRTs required time to get from the end of a line to the beginning of the
next. Therefore each line of video consists of active video portion and a
horizontal blanking interval. Even more time is needed for the CRT gun to
transition from the end of the last line to the start of the first, requiring each
frame to have a vertical blanking interval.
To reduce flicker, each frame is divided into two fields: odd and even
EECS150 Lab Lecture #7
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Digital Video (3)
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Colors
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Usually represented as red, green and blue
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In the digital domain we could transmit 8 bits
for each RGB component.
Transition from Black & White
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Kept compatible with old TV sets
Added separate color or “Chroma” signals
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Y: Luma (Traditional Black and White)
Cr: Chroma Red (New color signal)
Cb: Chroma Blue (New color signal)
EECS150 Lab Lecture #7
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Digital Video (4)
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Chroma Subsampling
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Human eye is more sensitive to Luma than
Chroma; use this to save space and bandwidth
RGB 4:4:4
Y CR CB 4:4:4
4:2:2 (ITU-601)
4:2:0 (MPEG-1)
4:2:0 (MPEG-2)
R0 R1
Y0 Y1
Y0 Y1
Y0 Y1
Y0 Y1
R2 R3
Y2 Y3
Y2 Y3
Y2 Y3
Y2 Y3
G0 G1
CB CB
CB 0-1
G2 G3
CB CB
CB 2-3
B0 B1
CR CR
CR 0-1
B2 B3
CR CR
CR 0-1
CB 0-3
CB 0-3
CR 0-3
CR 0-3
EECS150 Lab Lecture #7
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Checkpoint 2 (1)
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Video Encoder
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Sets up NTSC framing
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Blanking, Start of Active Video (SAV),
End of Active Video (EAV)
Request Data & Display it
Monitor
EECS150 Lab Lecture #7
Outgoing Video
(S-Video Out Cable)
8b NTSC Video
(Complete)
32b NTSC Video
(No Blanking)
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Video
Encoder
ADV7194
Video Line & Pair
Address
Test
ROM
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Checkpoint 2 (2)
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Video Display Module
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Replaces the test ROM
EECS150 Lab Lecture #7
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Checkpoint 2 (3)
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Nintendo 64 game controller
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Black box handles communication between FPGA
and the controller
Your task is to give meaning to the button
presses.
Controllers will be handed out in lab next week
EECS150 Lab Lecture #7
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Administrative Info (1)
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Design Review Policy Clarification
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Please come prepared
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We can’t help you if you haven’t taken a good look at the
spec and datasheet.
Turn in a copy of design documents at beginning
of lab
Do not use diagrams provided in the spec
Use Visio to make your diagrams
Lenient grading this time, but not for future
checkpoints.
EECS150 Lab Lecture #7
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Administrative Info (2)
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Design Review Process
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Walk YOUR LAB TA through your module
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Schematic
Bubble-and-arc
Top-down design with interconnections
Timing diagrams when appropriate
Errors will be pointed out, but corrections are left
up to you
Ideal duration: 10 minutes
Convince us you know what you’re doing!
EECS150 Lab Lecture #7
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Administrative Info (3)
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Pick up a mic after lab lecture if you
didn’t get one in lab this week.
Choose a team name (no more than 8
characters).
EECS150 Lab Lecture #7
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ITU-R BT.601
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Formerly, CCIR-601.
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Designed for digitizing
broadcast NTSC
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Variations:
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line i: CB Y CR Y CB Y CR Y
line i+1: CB Y CR Y CB Y CRY
Effective Bits/Pixel:
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4:2:0 Chroma Subsampling
PAL (European) version
Frame Rate
29.97 /sec
Scan
Interlaced
Chroma
subsampling
4:2:2
2:1 in X only
Coincedent
Bits per
component
8
Effective
bits/pixel
16
Component streaming:
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National Television System
Committee
Active Frame 720 x 507
Size
4 components / 2 pixels =
32/2 = 16 bits/pixel
EECS150 Lab Lecture #7
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FIGURE 1
Composition of interface data stream
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Active
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Blanking
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SAV/EAV: 4B/4B
Black filler
857
(863)
0
1
2
Chrominance
data, CR
359
360
368
( 366 )
0
1
Chrominance
data, CB
359
360
368
( 366 )
0
1
Replaced by
timing reference
signal
Pixels/Line: 720
Lines/Frame:507
First sample
of digital active line
Replaced by
digital blanking data
Replaced by
timing reference
signal
CB 0
Y0
CR 0
Y1
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736
(732)
CB 368(366)
Y 736(732)
CR 368(366)
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Pixels/Line: 858
Lines/Frame:525
Frames/S: 29.97
Pixels/S: 13.5M
718 719 720 721
CB 359
Y 718
CR 359
Y 719
CB 360
Y 720
CR 360
Y 721
Details
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Luminance
data, Y
Sample data
for OH instant
CB 359
Y 718
CR 359
Y 719
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Last sample
of digital active line
Y 855(861)
CB 428(431)
Y 856(862)
CR 428(431)
Y 857(863)
CB 0
Y0
CR 0
Y1
ITU-R
BT.656 (1)
Start of
active video
End of
active video
Timing reference signals
Note 1 – Sample identification numbers in parentheses are for 625-line systems where these differ from
those for 525-line systems. (See also Recommendation ITU-R BT.803.)
D01
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EECS150 Lab Lecture #7
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ITU-R BT.656 (2)
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Odd Field (262 Lines)
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Even Field
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Total: 262 Lines
6 Vertical Blanking
254 Active
2 Vertical Blanking
Total: 263 Lines
7 Vertical Blanking
253 Active
3 Vertical Blanking
EECS150 Lab Lecture #7
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ITU-R BT.656 (3)
P9
P8
P7
P6
P5
P4
P3
P2
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b1
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b1
F
V
H
E[3]
E[2]
E[1]
E[0]
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SAV Header
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F: Field Select (0: Odd, 1: Even)
V: Vertical Blanking Flag
H: EAV/SAV Flag (0: SAV, 1: EAV)
E[3]=V^H, E[2]=F^H, E[1]=F^V, E[0]=F^V^H
EECS150 Lab Lecture #7
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Video Encoder (1)
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Analog Devices ADV7194
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Supports ITU-R BT.601/656
S-Video and Composite Outputs
I2C Control (We will give this to you)
EECS150 Lab Lecture #7
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Video Encoder (2)
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Signal
Width Dir
Description
VE_P
10
O
Outoing NTSC Video (Use {Data, 2’b00})
VE_SCLK
1
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I2C Clock (For Initialization)
VE_SDA
1
O
I2C Data (For Initialization)
VE_PAL_NTSC
1
O
PAL/NTSC Mode Select (Always 1’b0)
VE_RESET_B_
1
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Active low reset (~Reset)
VE_HSYNC_B_
1
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Manual Control (Always 1’b1)
VE_VSYNC_B_
1
O
Manual Control (Always 1’b1)
VE_BLANK_B_
1
O
Manual Control (Always 1’b1)
VE_SCRESET
1
O
Manual Control (Always 1’b0)
VE_CLKIN
1
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Clock (27MHz, Just send Clock)
EECS150 Lab Lecture #7
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Video Encoder (3)
10/12/2007
Signal
Width
Dir
Description
Clock
1
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Clock input (27MHz)
Reset
1
I
Reset input
DIn
32
I
Requested Data from ROM
InRequest
1
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Request Data from ROM
DIn will be valid after rising edge
InRequestLine
9
O
Line of Video ({Line[7:0], Field})
The ROM will return a pixel from this line
InRequestPair
9
O
Pair of Pixels
The line will return data for this pixel pair
EECS150 Lab Lecture #7
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Video Encoder (4)
General Video Encoder Block Diagram
V FSM
Monitor
Outgoing Video
(S-Video Out Cable)
32b Clipped YCrYCb
(0x10≤Data≤0xF0)
Blank
Gen
(Mux)
10b NTSC Video
(Complete)
Data
Clip
IOReg
32b NTSC Video
(No Blanking)
Blank Control
ADV7194
I2C
Control
I2C Clock & data
H FSM
I2C Done
VCount
I2C Clock & data
Horizontal &
Vertical Count
Video Line & Pair
Address
Test
ROM
HCount
VideoEncoder
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EECS150 Lab Lecture #7
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Video Encoder (5)
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Basic Design
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Stream EAV, Blank, SAV, Active Lines
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Generate EAV/SAV/Blank using a mux
Register output data (Timing reasons)
Request Incoming Data
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Request it the cycle before you need it
Must be clipped
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Minimum data is 0x10
Maximum data is 0xF0
Otherwise it will appear to be blanking signals
EECS150 Lab Lecture #7
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Video Encoder (6)
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Testing
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Test thoroughly
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Simulation is difficult with test ROM
Try using values which count, so you can see it
Design your testbench early
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Perhaps one partner should design the module,
one should design the testbench
Ensure that you test corner cases
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First and last lines
Off-by-one errors in counters
EECS150 Lab Lecture #7
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I2C (1)
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ADV7194 Initialization using I2C
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Requires only 2 wires
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Runs at up to 400kHz
Bidirectional Communication
Given to you
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Serial Data (Bidirectional)
Clock (Driven by master)
Complicated to get right
Hard to debug
EECS150 Lab Lecture #7
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I2C (2)
Physical Protocol
Data
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Endpoint B
10kΩ Pullup
10kΩ Pullup
EECS150 Lab Lecture #7
DOut
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Enable
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Open collector
unidirectional bus
Driven by master
May be pulled low to
stall transmission
DIn
Clock
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Open collector
bidirectional bus
Driven by sender
DOut
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Endpoint A
Enable
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Bidirectional Open Collector Bus
DIn
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I2C (3)
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Protocol
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Start Condition
Address
Address Acknowledge
Data Transfer
Data Acknowledge
Stop Condition
EECS150 Lab Lecture #7
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I2C (4)
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Arbitration
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Anyone can drive bus at any time
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No central arbiter
No short circuits (Impossible in open collector)
Decentralized Arbitration
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Check data bus against value you’re sending
Mismatch means someone else is transmitting
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So let them finish, and then try again
Inherently gives preferences to accesses with
more 1’b1s in them
EECS150 Lab Lecture #7
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Video Display (1)
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EECS150 Lab Lecture #7
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Video Display (2)
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Replaces test ROM
Defines the “look and feel” of the
project
Do not start this part until you have
completed the video encoder!
Must be able to display text
EECS150 Lab Lecture #7
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CharROM.v
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Character ROM
Takes an encoded ASCII character and
outputs a dot matrix
Your responsibility to figure out how to
convert dot matrix to video data
EECS150 Lab Lecture #7
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RAM.v
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Synchronous 256-byte memory module.
Use this to store characters.
No reset signal.
EECS150 Lab Lecture #7
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User Input Parser
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We’re giving you a module that tells you which
buttons are pressed.
Use buttons to determine:
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Speaker volume
Speaker mute
Mic volume
Mic mute
Wireless channel
Region focus
More! (In a later checkpoint)
Keep module clean and extensible. You will need add
to it later.
EECS150 Lab Lecture #7
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Tasks for Video Display (1)
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Split screen into three distinct regions
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When determining the width and height of
these regions, keep in mind the following
restrictions:
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One for users in the channel
One for users you’re connected with
One for console output
No more than 8 users displayed in region 0.
No more than 8 users displayed in region 1.
User names are no more than 8 characters long.
EECS150 Lab Lecture #7
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Tasks for Video Display (2)
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Graphically display speaker and mic
volume at the bottom of the screen.
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Handle mute
Display wireless channel at lower right
hand corner of the screen.
Highlight appropriate region based on
the Focus value.
EECS150 Lab Lecture #7
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Tasks for Video Display (3)
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Display your team name (no more than
8 characters) at the top of the screen.
Store and display 8 other user names of
your choice in region 0.
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Registry of users should be robust enough
to handle adding/dropping users.
Choice of colors and aspect ratio up to
you.
EECS150 Lab Lecture #7
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More Information
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Documents Page of the Website
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Video in a Nutshell
ADV7194 Datasheet
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ITU-R BT.656 & ITU-R BT.601 Standards
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10/12/2007
Complete ADV7194 reference
Complete video standards
I2C Bus Specification
READ THE DATASHEETS!
EECS150 Lab Lecture #7
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Questions?
10/12/2007
EECS150 Lab Lecture #7
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