Transcript SystemC Users Forum Japan February 1, 2001 Agenda  Why SystemC ?  Organizational Update  The Growing SystemC Marketplace  SystemC v2.0 Roadmap  v2.0

SystemC Users Forum Japan
February 1, 2001
Agenda
 Why SystemC ?
 Organizational Update
 The Growing SystemC Marketplace
 SystemC v2.0 Roadmap
 v2.0 Capabilities and Benefits
 v1.2beta Capabilities and Benefits
2
SystemC Mission - Model Concept to RTL
Environment
Specify
Product
Architecture
Hardware
Software
Co-Design
Implement
Co-Verify
Verify
3
Code
Reuse
IP
Reuse
IP
SW Code
Implement
Verify
Design
HW Design
Reusable
IP
Integration
Implement
Verify
Concept
to
RTL &
Software
RTL
to
GDSII
SystemC - Enabling System Level Design
System
System
Level IP
RTL
HW
Implementation
Soft IP
Verification &
Analysis
SW
Implementation
Physical
C-Compiler
Hard IP
4
Why SystemC ?
Stan Krolikoski
Vice President
System Level Design Group
Cadence Design Systems
The Evolution of SystemC
Full System Specification
2.x/3.y
Algorithm
Design
System Architecture
Design Space
Exploration
2.0
Links to Verification and
Implementation
1.0
Advanced & Functional Verification
Synthesis / Place & Route etc.
6
We’ve been here before
 During the 1960/1970’s, many SW languages were created
– Lack of compatibility between SW modules became a real issue
Even single languages had multiple dialects
– Eventually C/C++ became the de facto standard
Others still being used, e.g., Ada, Lisp,...
 During the 1970/1980’s, multiple HDLs started to be developed
– Strong actions by the US department of defense helped create VHDL
– Market dominance helped Cadence establish Verilog
– Not many alternative HDLs are being used today
But we still ended up with two!
Let’s not repeat the past!
7
We are at a fork in the road
 System level design is becoming necessary
– The size, speed and complexity of the latest designs require a
higher level of abstraction than RTL
 Good system languages will be crucial in enabling
system-level design
– Even in systems that are GUI based
 Therefore, we need to develop system languages,
but….
 Can we afford to have many system level languages?
NO!!!!!!
8
There must be A language for system design
 We cannot get into the mess we were with SW languages
 We cannot even afford to have two dominant languages
as in the HDL world
 We need a single language that can serve as
– A “backbone” for system-level design tools
– A common format for system level IP exchange and tool
interoperability
 Other languages may still be used for specialized tasks,
but we need a common system-level language
That Language is SystemC
9
We need everyone’s help!
 SystemC must meet the needs of both users and
vendors
 This requires a strong cooperation between companies
– Even between strong rivals-- we are all in this together
 The SystemC group already has a good mixture of
vendors and users from around the world
 But we need more members, and we need more user
participation in evolving SystemC
If SystemC is OUR language, then WE must develop it
10
Organizational Update
Pete Hardee
Director, Product Marketing
CoWare
Open SystemC Initiative Delivers !
 Fast Innovation
– SystemC v2.0 Specification
major step in system level modeling
cross industry contributions
- Cadence, CoWare, Fujitsu, Motorola, STM, Synopsys
– SystemC v1.2 beta Software
 Common, Open Industry Solution
– OSCI incorporated NOW as non profit organization
– OSI-compliant Open Source license
 Broad industry adoption and success !
12
Open SystemC Initiative Steering Group
13
Strong User Adoption and Success
 Over 7,000 Licensees at over 500
companies/institutions
 Over 12,000 successful downloads of SystemC
source code
 SystemC successes presented at numerous
venues
– DATE, FDL, HDL Con, IP/SoC, ASP/DAC, ESP, …
– CSELT, Infineon, Siemens, STM, ...
 Commercial projects featured on web based
SystemC Forum at www.systemc.org
14
14000
Downloads
12000
Licensed Users
10000
SystemC v1.0/1.1beta
Released
8000
6000
4000
15
Nov-00
Sep-00
Jul-00
May-00
Mar-00
Jan-00
0
Nov-99
2000
Sep-99
Users/Downloads
A year of Strong SystemC Adoption
SystemC Solutions
Kevin Kranen
Director, Strategic Programs
Synopsys, Inc.
SystemC Value Chain is Building
 Over 25 SystemC-based EDA, IP and service
products announced or released by:
 See http://www.systemc.org/products.html for
exhaustive list
17
SystemC Product Briefs
All product claims contained within
are provided by the respective
supplying company.
Blue Pacific Computing
BlueWave
 Blue Pacific’s BlueWave is a simulation GUI,
including waveform viewer that can be used to
view and analyze VCD results on Linux, Unix,
Windows, including SystemC outputs. BlueWave
Student version is free.
 Enables visualization and analysis of SystemC
modeling
 Contact Blue Pacific at: [email protected] of find
us on the web at www.bluepc.com, phone: (858)
484-7500
19
Blue Pacific Computing
SystemC
Classes
 Three-day SystemC On-Site Classes focussing
on SystemC for VHDL and Verilog Designer with
additional two-day foundational course on C and
C++
 Teaches SystemC modeling and simulation to
people with traditional Verilog or VHDL
background.
 Contact Blue Pacific at [email protected] or find
us on the web at www.bluepc.com, phone: (858)
484-7500
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SPW 4.6-SystemC 1.0
Co-simulation
True Co-simulation
– Synchronization maintained between
Full System Specification
Block Level
Specification
SPW Floating Point
Algorithm Analysis
SPW Fixed Point
Algorithm Analysis
Software
Development
Hardware
Development
IP Block Authoring
SPW
DSP Behavioral Specification
SPW/HDS and SystemC simulators
– Debugging may be done in either SPW
and/or in SystemC debugger
– Breakpoints can be set in either system
– Will work with any SystemC 1.0 simulator
SPW HDS Block Implementation
Implementation Flow
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SystemC 1.0
SYSTEMSIM™
 Multilingual simulator, supporting Verilog, Superlog, C,
C++ and SystemC, without interfaces or co-simulation
C / C++ HDL
Superlog
SYSTEMSIM
SystemC
 Allows SystemC models to be called from alternative
language constructs to provide a fast, usable method
to solve alternative language IP and legacy code issues
 Contact Co-Design Automation, Inc,
www.co-design.com, [email protected]
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Vip Library: a wide set of customizable and
flexible system level Intellectual Property Soft
Cores to answer Information and Communication
Technologies Product requirements
Availability of SystemC Core description to stress
architectural exploration before HW/SW
partitioning is performed.
Contact CSELT S.p.A, [email protected],
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CoWare N2CTM
 CoWare N2C - Napkin to Chip in Half the Time. Full
SystemC Co-Design Environment featuring:
– Specification
– Partitioning
– Co-implementation
– Co-verification
}
Analysis at every stage
 Read in and write out SystemC from CoWare N2C
– CoWareC or SystemC in
– CoWareC, SystemC, VHDL and Verilog out
 Visit www.CoWare.com
24
CoWare N2C System-Level
Design Flow
Algorithms, Control
and Testbench
ANSI C/C++, SystemC
or CoWare C
Architecture
Function
Behavioral C/C++
System Design
and Partitioning
Executable
Implementable Spec
HW Design
Interface
SW Optimization
RTLC
Generate
HDL
Synthesis
Testbench
Interface Synthesis
Cycle-Accurate C/C++
HW-SW Co-design
and Multi-level
Co-verification
SW Image + RTL
"Traditional"
HW-SW Co-verification Implementation
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IP and Performance
Models
Databahn Memory
Subsystem Generator
 Databahn, an on-line tool, generates
synthesizable memory controller cores and
automatically produces all C-level verification
support for the associated memory subsystem
 Produces SystemC models of these cores
 Contact: Steven Shrader (208) 376-6030,
[email protected] or visit our website at
www.denalisoft.com
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(in-System Algorithm Verification Engine)
 Dynalith’s iSAVE technology combines the benefits of Cbased design with the ability of H/W emulation running with
the real target system at real speed.
 iSAVE framework supports hardware models in high-level
programming languages including SystemC.
 Contact Dynalith Systems (www.Dynalith.com) at:
– [email protected] (H.Q.)
– [email protected] (World Wide)
– [email protected] (USA)
– [email protected] (Japan)
27
iSAVE design flow
with SystemC
Algorithm in SystemC
Automated iSAVE Design Environment
PrepIFM
(designates interface modules and protocols)
An example of MPEG2 Decoding
iscconfig
PSGbuilder
Synthesizer
PAGbuilder
Synthesizer
Modified
SC code
Compiler
TIE
Configuration
Data
Executable
Code
 Proven SystemC-based architectural exploration
 Interactive C-to-HDL design flow
 Optimized implementation
 High level design re-use
 ASIC and FPGA
 Silicon proven for :
– ultra-low power applications
– telecom base-band processing
– consumer speech processing
 Contact [email protected]
29
Outputs
Inputs
 Automatic SystemC-to-HDL
 What You Write Is What You Get
 Produces hierarchical Mealy Machine
 VHDL and Verilog output
 ASIC and FPGA
 Automatic test-bench generation
 Contact [email protected]
 http://www.frontierd.com
Compute process
(combinatorial)
Compute
Update
Update process
(sequential)
Clk
30
Reset
Enable
 Fixed-point data types contributed to SystemC
 Bit-accurate modeling
Abstract Base Class
 Any width and precision
Fix<w,d>
Ufix<w,d>
 Overflow and quantization behavior
Int<w>
Uint<w>
 Analysis and statistics
 For LINUX, SUN Solaris, Microsoft Windows, HP-UX
 For Microsoft, Borland, Sun, HP and GNU C++ compilers
 Downloadable from http://www.frontierd.com
 Contact [email protected]
Fix<5,2>
Ufix<5,2>
S
Int<5>
S
31
Uint<5>
VStation Co-Modeling
 Ultra high-performance Co-Modeling between behavioral
models running on a workstation and implementation
models running on IKOS VStation.
– Based on the world’s first high-performance transaction
interface
– System verification productivity at emulation speed
 Enables SystemC models to be used in conjunction with
emulation
– Bring the value of high performance emulation earlier in the
verification process
– Utilizing your SystemC environment throughout the design
cycle
 http://www.ikos.com
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Design Flow
Closing The Verification
Productivity Gap
Untimed
C
Run 4 seconds
real-time
verification in…
5 minutes
Overnight
Mixed-Level
C
1.5 months
RTL HDL
1.25 years
Gate-Level
Real
Hardware
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4 seconds
Visual SLD
 Systems-Level Design environment for defining and
verifying system architecture, Hardware/Software
co-verification, Register Definition. Includes
Embedded Systems support, Complete code-coverage
debug and analysis. Built upon the strongest graphic
entry tool in the industry, Visual HDL. Truth-table,
flowchart, Finite-State Machine, Block Diagram
 Language design via SystemC, C/C++, Verilog, VHDL
 www.innoveda.com, or (800) 223-8439
34
Visual SLD
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TestBencher Pro
 Graphical environment for generating bus-functional models
 TestBencher generates SystemC test benches from language
independent timing diagrams.
– Generates all the class code for each diagram, including port
mappings and sensitivity lists
 Visit www.syncad.com and download an evaluation version
 Contact SynaptiCAD at [email protected] or 800-804-7073
36
TestBencher Pro
Generates SystemC Code
CoCentricTM Tools
Architecture
Functionality
CoCentricTM
System Studio
SystemC
CoCentricTM
SystemC Compiler
+
a.out
CoCentricTM
System Studio
HW/SW Co-Design propelled by SystemC
 integrated system level tool for
… performance analysis of
system architecture and function
… concurrent design of HW and SW
at multiple levels of abstraction
 Contact [email protected] or visit
www.synopsys.com for more information
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CoCentricTM
SystemC Compiler
Complete synthesis from SystemC to hardware
 C/SystemC synthesis
… refine & synthesize from C/C++ executable spec
… path to FPGAs for system designers
… powerful constructs for RTL designers
 Complete
Behavioral
or RTL
CoCentric
SystemC Compiler
… behavioral & RTL
… SoCs, ASICs, FPGAs
 Contact [email protected] or visit
www.synopsys.com for more information
40
Design Compiler
Physical Compiler
FPGA Compiler II
SystemC-HDL Co-Simulation
HDL
Interface
Library
 VCS, Scirocco, MTI-VHDL
 Model import & export
 Contact [email protected] or visit
www.synopsys.com for more information
41
HDL
SystemC-VERA I/F
 High performance, direct kernel interface for integrating
VERA with SystemC
 Uses the powerful, verification related features in VERA
to verify system designs described in SystemC
 Contact [email protected] or visit the website at
www.synopsys.com for more information
42
TT VTOC
 Converts from Synthesisable Verilog to C/C++
– Compiles multiple Verilog modules totalling up to about
100K gates into one large, highly-efficient, cycle-based C
or C++ implementation.
– Provides a mechanism for efficient linking of separately
compiled modules.
– Main applications are fast simulation and generation of a
system-level emulator for the software team.
 SystemC is one of the output formats
 Web site is www.tenisontech.com
43
SuperC™
 A very fast SystemC Simulator that writes a
highly compressed data format. This wave form
data is compressed by 15-50X and can be
displayed almost instantly by the Undertow
waveform viewer regardless of file size.
 Veritools provides the SuperC™ C++ class
compile library for the Veritools SuperC™
simulator
 Contact Veritools at [email protected] or
Robert Schopmeyer at [email protected]
44
Undertow Suite
 A waveform viewer and Source Code debugging program
for the SystemC/SuperC™ Simulator that reads the the
highly compressed data format that is written directly by
the SuperC™ simulator. This waveform data can be
displayed almost instantly by the Undertow waveform
viewer regardless of file size while providing linkage and
synchronization with the SystemC source code.
 Undertow uses the highly compressed “Fast file” format
from SuperC™ while providing Source Code debug
facilities for SystemC Source Code.
 Contact Veritools at [email protected], or Robert
Schopmeyer at [email protected]
45
Undertow
 A very powerful waveform viewer for the
SystemC/SuperC™ Simulator. This wave form data can
be displayed almost instantly by the Undertow
waveform viewer regardless of file data size
 Undertow uses the SystemC native waveform data or the
highly compressed “Fast file” format from SuperC™
 Contact Veritools, Inc. at [email protected] or
Robert Schopmeyer at [email protected]
46
From Virtual Prototyping
to SystemC
 Evaluate, experience, and design embedded IP
platforms from your browser!
 Explore pre-configured embedded platforms,
create high-level system models, and generate
SystemC to link your designs to implementation.
 For more information contact [email protected] or
visit our web site at www.virtio.com.
47
Training:
 Modeling with SystemC.
– Introduction to modeling with C/C++ and the SystemC
class libraries. Learn how to write, compile, execute, and
debug system and hardware descriptions with SystemC.
 SystemC for High Level Synthesis(HLS)
– Learn HLS concepts, SystemC coding style required for
HLS, testbenches and RTL co-simulation.
 For more information or for class schedules email to
[email protected], or visit website at www.whdl.com
48
Language Rule Checker
 Complete language rule checker
 Performs netlist, general coding style and
synthesis coding style checks on your
SystemC code.
 Contact Willamette HDL, [email protected]
49
Open SystemC Initiative Delivers !
 Fast Innovation
– cross industry contribution
 Common, Open Industry Solution
– OSCI incorporating NOW as non profit organization
– OSI-compliant Open Source license
 Broad industry adoption and success !
50
SystemC v2.0 Roadmap
Takashi Hasegawa,
Director of Strategic Software
Systems, World Wide System LSI
Technologies - Fujitsu
SystemC v2.0 Innovation
 SystemC v1.0
– RTL & behavioral level modeling (HDL & beyond)
– integrated with higher level C/C++ functional modeling
 SystemC v2.0
– provides higher levels of abstraction
– enables modeling of HW / SW interaction
– flexible communication channel refinement
52
SystemC Evolution
SystemC
v2.0 LRM
v2.0 Detailed
Spec
v2.0
beta
v1.2
beta
• v2.0 model of time
• Dynamic sensitivity
• Code fixes
Feb
2001
53
New SystemC
Foundation for Systems
• Channels & Events
• Comms Refinement
• Backward compatibility
Q2
2001
v2.0
Production
• User Validation
Q3
2001
SystemC Release Roadmap
 1.0 - Hardware Design Flow
– RTL and Behavioral Hardware Modeling
 1.x - Master-Slave Communication Library
– RPC-based untimed & timed functional modeling down to
RTL for bus protocol based systems
 2.0 - System Design Flow
– General purpose communication and synchronization
– Communication Refinement
– Multiple, customizable models of computation
54
SystemC Release Roadmap (cont)
 2.X - Extensions to System Design Flow
– Dynamic thread creation, fork / join
– Interrupt / abort for behavioral hierarchy
– Performance modeling support
– Timing specification and constraints
 3.X Software Design Flow
– Abstract RTOS modeling
– Scheduler modeling
 4.X - Analog / Mixed Signal Systems Modeling
55
SystemC 2.0 Specification
and Benefits
Thorsten Grötker
Synopsys, Inc.
Motivation
 SystemC 1.0
HW modeling (RTL and behavioral)
 SystemC 2.0
extend scope to System-Level Modeling
 System-Level Modeling
– functional models
– transaction-level platform models
– high-level architecture models
57
How do we achieve this?
 We use a flexible and powerful Model of
Computation (MoC).
 A MoC is characterized by
– the model of time employed,
– the rules for process activation, and
– the supported means of communication.
58
MoC: Model of Time
 SystemC 1.0
Relative floating-point model of time (double)
 SystemC 2.0
Absolute (64 bit) unsigned integer model of time
 Why?
– Avoid finite precision effects, e.g. underflow
– Use absolute model of time: define time units
(IP exchange)
59
MoC: Rules for Process Activation
 SystemC 1.0
– Static sensitivity
Processes are made sensitive to a fixed set of signals during
elaboration
 SystemC 2.0
– Static sensitivity
– Dynamic sensitivity
The sensitivity (activiation condition) of a process can be
altered during simulation (after elaboration)
Main features: events and extended wait() method
60
Events
 Events are objects (sc_event)
 Events can be notified (sc_event::notify())
 Channels use events
(Signals use events to indicate value changes.)
 Modules can use events
 Processes can wait for events
(Dynamic sensitivity)
61
Waiting
wait();
// as in SystemC 1.0
wait(event);
// wait for event
wait(e1 | e2 | e3); // wait for first event
wait(e1 & e2 & e3); // wait for all events
wait(200, SC_NS);
// wait for 200ns
// wait with timeout
wait(200, SC_NS, e1 | e2);
wait(200, SC_NS, e1 & e2);
62
MoC: Communication
 SystemC 1.0
– Fixed set of communication channels (sc_signal, …)
and ports (sc_in, sc_out, …).
 SystemC 2.0
– user-defined
interfaces
channels
ports
Define your own bus,
message queue, … etc.
– richer set of predefined channels
(HW signals, FIFO, semaphore, mutex, …)
63
Interfaces and Channels
 An interface is a set of methods implemented by
a channel.
struct write_if : public sc_interface
{
virtual void write(char) = 0;
virtual void reset() = 0;
};
struct read_if : public sc_interface
{
virtual void read(char &) = 0;
virtual int num_available() = 0;
};
 A channel can implement multiple interfaces.
64
Ports
 Ports …
– connect modules and channels
– specify the required interface (e.g. sc_port<IF>)
– give modules (processes) access to interface methods
sc_port<write_if> p;
void some_process() {
...
p->reset();
p->write(‘X’);
...
}
65
Primitive and Hierarchical Channels
 Primitive channels
– are atomic entities
– have no visible internal structure
– can use request-update scheme (HW signals)
 Hierarchical channels
– are modules that implement interfaces
– can have ports
– can contain processes, modules, and channels
 Both implement interfaces
66
Architecture of SystemC 2.0
Methodology-specific and
User-Defined Channels
Elementary channels
(signals, FIFOs, …)
Channels, Interfaces, Ports
Events, Dynamic Sensitivity
SystemC Scheduler
67
Model of Computation
 Very powerful and flexible
 Supports well known MoCs such as
– discrete-event models
RTL / behavioral HW models
network modeling
transaction-level SoC platform modeling
– Kahn process networks
static multi-rate data flow
dynamic data flow
– Communicating Sequential Processes
68
Benefits of SystemC v2.0
 Enables, fast smooth system design
– Communication can modeled and refined independent of
function
 Supports virtually all system modeling needs
– Flexible semantic foundation additions support most
models of computation within one environment
– Leverages all existing v1.0 and v1.1beta capabilities
 Broadly applicable, “best of breed” solution
– Designed by 12 experts from six different EDA and System
IC companies
– Tuned for both EDA tool and IP use
69
System design capabilities
in v1.2beta
Dündar Dumlugöl
Director of Engineering, CoWare
Master-Slave communication library
 Targets systems with bus protocol communication
SoC’s with cores, DSP’s, peripherals & custom HW
 Enables automatic synthesis of bus interfaces
 Complete path from Functional to RTL
71
Abstractions
Matlab
SpecC
SDL
Esterel
Others
Functional decomposition
SystemC
UTF
Untimed Functional
Assign ‘execution time’
Design Exploration
Performance Analysis
HW/SW partitioning
TF
Timed Functional
HW / SW Partition
Architectural mapping
Refine communication
Task Partitioning
Abstr.
RTOS
BCA
Bus Cycle Accurate
Refine behavior
Target RTOS/Core
Software
72
RTOS
RTL
Cycle Accurate
Hardware
Gradual Refinement of the Design
Key to the methodology is that a design may be refined in a gradual step-wise fashion,
rather than in one giant step… it need not be “all or nothing”.
UTF
UTF
UTF
Simulation
UTF
Details added
to portions of
the system.
UTF
UTF
UTF
TF
Simulation
UTF
TF
TF
BCA
RTL
Simulation
UTF
73
RTL
Key modeling paradigms
 Abstract functional communication
Point-to-point & multi-point sequential channel
Abstract model for bus communication
 Concurrent communication & synchronization
 Cycle accurate bus protocol communication
74
Point-to-Point abstract communication
Equivalent to function call but without
function pointer
P1
P2
Structure is
key for re-use
Concurrent process
75
Slave process
Specify a communication through …
 Initiator (master / slave ports)
 Direction of data transfer (in-, out-, inout ports)
 Data type
 Index (=address)
 Channel / transaction configuration
– Type of communication (e.g.blocking with time out)
– Return status (pass/ fail …)
 Bus protocol at the cycle accurate level
76
Multi-point abstract communication
A
B
77
A11
A12
A21
A22
A13
Example: sequential execution thread in
a system
Keyboard
Control
Processor
cmd
cmd
op1
op1
op2
op2
result
Display
display
78
Sequential & concurrent communication
in a hierarchical channel
BW: blocking write with time-out
BR: blocking read with time-out
Producer
Consumer
BW
bWrite bRead
FIFO
clk1
clk2
FIFO channel
79
BR
Example: full-handshake protocol
Producer
link
Consumer
Full Handshake protocol
Producer
clk1
80
Req
Ack
Data
Consumer
clk2
Dynamic thread library (prototype)
 For future SW flow
– Enables fork & join functionality
– Foundation for future RTOS
 Create thread at run time
 Start another thread with process id
 Stop thread (self)
 Kill another thread
 Get parent id
81
Benefits of master-slave library
 HW/SW co-design from Functional to RTL
 Enables automatic synthesis of bus interfaces
 Enables fast IP embedding & HW-SW partitioning
 Orders of magnitude faster than RTL verification
82
Panel Session
Moderator:
Masaharu Imai (Osaka University)
Panelist names and titles
 EDA Tool Provider
– Shusaku Yamamoto
– Kiyoshi Ikuta
– Junji Nakano
Cadence
CoWare
Synopsys
 User
– Takashi Hasegawa
– Masamichi Kawarabayashi
– Masaru Kakimoto
84
Fujitsu
NEC
SONY