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SAGA : SystemC Acceleration on GPU Architectures Presenter: Ming-Shiun Yang Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE Sara Vinco(Italy), Debapriya Chatterjee(USA), Valeria Bertacco(USA), Franco Fummi(Italy) 1 2013/01/21 SystemC is a widespread language for HW/SW system simulation and design exploration, and thus a key development platform in embedded system design. However, the growing complexity of SoC designs is having an impact on simulation performance, leading to limited SoC exploration potential, which in turns affects development and verification schedules and timeto-market for new designs. Previous efforts have attempted to parallelize SystemC simulation, targeting both multiprocessors and GPUs. However, for practical designs, those approached fall far short of satisfactory performance. This paper proposes SAGA, a novel simulation approach that fully exploits the intrinsic parallelism of RTL SystemC descriptions, targeting GPU platforms. By limiting synchronization events with ad-hoc static scheduling and separate independent dataflows, we shows that we can simulate complex SystemC descriptions up to 16 times faster than traditional simulators. 2 Original SystemC simulation 3 Use scheduler to dispatch all processes to one core. Sequential processing. The growing complexity of SoC designs is having impact on simulation performance. Heavy overhead Code modification [1,4,9,10] Parallel SystemC Environment [7]CUDA Programming Guide General purpose programming interface This Paper 4 [3]HIFSuite Mapping SystemC to CUDA Compute Unified Device Architecture (CUDA) An interface is proposed to GP-GPU programming GPU is a co-processor capable of executing many threads in parallel Mapping SystemC to CUDA : SystemC 5 HIFSuite: sc2hif HIF file HIFSuite: hif2C C file CUDA SAGA Exploit scheduling to eliminate the need of frequent synchronization. Carve independent dataflows and then mapped to distinct threads and processors. (Parallel execution) SystemC 6 HIFSuite: sc2hif HIF file Traditional Simulator SAGA HIF file modified HIFSuite: hif2C C file Proposed Simulator (SAGA) CUDA 7 8 Queue Current dataflow list P8 P8 Queue ≠ Empty, pop P8 Queue Current dataflow list P6 P7 P8 P6 Queue ≠ Empty, pop P6 Queue Current dataflow list P7 P1 P2 P7 P6 P8 Queue ≠ Empty, pop P7 Queue P1 Current dataflow list P2 P3 P4 P8 P6 P7 Current dataflow list P8 9 P6 P7 P1 P2 P3 P4 10 -1 2 -1 2 -1 1 0 -1 1 1 -1 0 0 0 0 0 1. Set all leaf nodes to 0 level 2. Set all non-leaf nodes to -1 level 3. if parent level < child level, parent level = child level +1 ex. P6’s level < P1’s level P6’s level = 0+1 =1 … 11 0 Column 3 : loc – line of codes Column 4 : Dataflows (#) – partition number of dataflows in step 2. Column 5 : Replicated processes / the maxmum amount of replication for these process 12 16 times faster than traditional SystemC simulator. 13 HIFSuite : A set of tools and APIs that provide support for modeling and verification of HW/SW system. SystemC 14 HIFSuite: sc2hif HIF file SAGA HIF file modified HIFSuite: hif2C C file CUDA 15 Proposed a parallel schedule method for SystemC simulator. A novel partitioning technique to carve independent dataflows mapped to distinct threads and multiprocessors. The time of translating SystemC to CUDA by HIFSuite is so long. 。They expect that a mature version could operate directly on SystemC source code (future work) This paper is good illustrate clearly Experiment result 。Achieve their goal (reduce the simulation time) 。Many analysis 。Compare with other works 16