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Presenter: Chun-Hao Wang

2020/4/27

ESL design and verification Virtual prototyping verification QEMU [1] SystemC RTL QEMU-System C [2][3] [6] [1] QEMU, a Fast and Portable [2] On the interface between QEMU and SystemC for hardware modeling [3] Dual-core virtual platform with QEMU and SystemC [4] SoC HW/SW Verification and Validation

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[5] A Practice of ESL Verification Methodology from SystemC to FPGA [6] Standard Co-Emulation Modeling Interface (SCE-MI) Reference Manual [4] [5] FPGA prototyping verification

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 There is an need for the EDA industry to meet the exploding verification requirements of SoC design teams. Existing standard verification interfaces were designed to meet the needs of design teams of over 10 years ago. A new type of interface is needed to meet the verification challenges of the next 10 years. SCE-MI 2.0 is a standard drafted by Accellera which consist of many members (ARM 、 Cadence 、 Synopsys 、 Nokia…). This standard extends the SystemVerilog Direct Programming Interface (DPI) since the traditional simulator APIs like programmable language interface (PLI) and VHDL PLI slow down emulators. The main components are Software side(C 、 SystemC…) 、 Hardware side(RTL 、 FPGA 、 ASIC…) and SCE-MI Infrastructure (as the physical bridge).

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Figure 1. SCE-MI Architecture

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 un-timed simulation environment with a cycle accurate simulation environment.

Figure 2. Hardware Side control clock

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 C Side generate the testbench to HDL Side

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Figure 3. HDL/C function call example

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 PC bridge and FPGA bridge is required  The MDK-3D and Workstation are communicate by TCP/IP socket FPGA FS MDK-3D PC bridge TCP/IP socket Coware testbench FPGA bridge B U S VS (SystemC) PM (RTL) Workstation

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 FPGA bridge handle following event  Bus read/write  VS VOB read  Clock information(align the FPGA clock)  Socket Message send/receive VOB Socket message FPGA bridge B U S VS clock

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 Need on-board Linux support to handle socket  Linux run a service loop handle the message from socket to PC bridge  Need a device driver to control PC bridge(mmap) FS FPGA cclock PC bridge MDK-3D B U S ARM11 Service loop Linux TCP/IP socket

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S/W H/W Root file System 3D Graphics TestBenches API(GLES2.0) Compiler Linux Kernel 2.6.28

3DG ES1.0device driver ARM Versatile platform baseboard Memory VIC ARM1136 SYSBUS PL110 LCD SC bridge (C/C++) QEMU IPC handshake Shared memory Patten Result QEMU bridge (SystemC) A H B VS (SystemC/RTL) FS (SystemC/RTL) Synopsys(CoWare) Platform Architect Pattern Result Testbench IP (SystemC) A H B VS (SystemC/RTL) FS (SystemC/RTL) Synopsys(CoWare) Platform Architect

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 This standard support the co-emulation extended from SystemVerilog  Testbenches not need changing between simulation and emulation.

 Logic bug will be found in early stage.

 This verification can be run on non-bus environment.

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