Transcript Usage of System C - Vienna University of Technology

Usage of System C
Marco Steffan
0215884
Overview
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Standard
Existing Tools
Companies using SystemC
Common Standards
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Open SystemC Initiative (OSCI)
IEEE 1666-2005 Standard SystemC
Language Reference Manual (LRM)
Members
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Intel, ARM, Cadence,
CoWare, Synopsys,
STMicroElectronics
Canon, NEC, Infineon
Tools
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Forte Design Systems: Cynthesizer
Synopsys: System Studio
Veritools (Verilator)
CISC Semiconductor Design+Consulting
GmbH: System Architect Designer (SyAD)
Mentor Graphics
Candence
Companies using SystemC
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Nokia
Infineon Technology AG
Motorola
Intel
HP
Texas Instruments
Nokia
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Modelling networks on mobile platforms
Basic block approach (like LEGO)
Combine blocks (SpaceWire)
Build own Network-Simulator from
scratch
Start with SystemC 2.0.1
Extended to mySystemC
Infineon Technology AG
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Impact of different Datatypes on
performance
Appropriate type-selection gains 2x and
more simulation speed improvements
Available libraries provide almost all
needed features
Gcc-version has almost no impact on
speedup
Motorola
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Early systems architecture exploration
Corner case study
Design change impact evaluation
Calls for Improvement
(Motorola)
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Enhance model components portability
Data flow interface
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Inter-module functional communication and
simulation flow control
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Generic TLM bus interface preserving accuracy and providing
flexibility in bus models selection
Off-module process triggering and dynamic parameters
sharing
User interface
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Model components configuration
Simulation result representation
User-friendly
Intel
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Modeling interconnect & non-processor components
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Architecture models (“Architect’s View”)
Functional models (“Programmer’s View”)
Above are mixed and integrated with processor
models for:
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Architecture exploration
Early software development
Early (post-Si) system validation readiness
Early RTL verification
 Testbench* and test development (with ESL DUT)
 Application of system-level stimulus
 Co-simulation
 Co-emulation
* Testbenches primarily developed in SystemVerilog
HP
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SystemC Usage
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RTL Verification
Modeling (UTF,TF, BA/CA)
System Simulation (no RTL)
FW development on SW
model
Architectural Verification
Deployment of System
Verilog
Applications
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Enterprise Level Servers
Embedded Processors
ASSP’s
Algorithms (FFT, DCT,
Wireless, etc.)
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Reasons for SystemC:
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Non proprietary, IEEE Std.,
LRM
Industry Support
TLM, AVM, SCV, etc.
Proven capabilities
Cost Effective
Calls for Improvement (HP)
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Mixed Signal Libraries
Topology / Configuration generation (similar to
generate function)
More Academic Proliferation
Keep entry price low (benefits start ups, small
companies)
More industry donations
Tools to support higher abstraction (formal
verification, advanced assertions)
Increase interactions with System Verilog(common
TLM API’s?)
Texas Instruments
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Usage Areas:
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High level architectural modeling (PV/PVT)
Low level architectural/SoC modeling (CC)
Synthesis (experimental)
Internal SystemC user group meetings
Bus models, CPU models, peripheral
models, configuration, statistics, debug
Call for Improvements (TI)
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SystemC has poor support for
asynchronous events
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Interrups/resets/power-downs
Cooperative co-routines/threads
For full support would require every
method and every thread to add async
events to their sensitivity lists
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Possible to use, but very inconvenient
Need kernel support
Conclusion
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Missing features / libraries
Still in initial stage
Not for every kind of simulation
Personal impression: „Would like to use,
but...“
Thank you!
References
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IEEE 1666 Standard
http://standards.ieee.org/getieee/1666/download/1666-2005.pdf
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Tools
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European SystemC Users Group
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http://www.asic-world.com/systemc/
SystemC Community
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http://en.wikipedia.org/wiki/Systemc
ASIC-World
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http://www-ti.informatik.uni-tuebingen.de/~systemc/systemc.html
Wikipedia.org
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http://www.asic-world.com/systemc/tools.html
http://www.systemc.org
Mentor Graphics
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http://www.mentor.com/products/