Transcript 162-Ball NAND and LPDDR2 MCP

Preliminary‡
Micron Confidential and Proprietary
162-Ball NAND and LPDDR2 MCP
Features
NAND and Mobile LPDDR2
162-Ball MCP
MT29RZxxxxxxxxxxxIxxxxx
Features
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Figure 1: MCP Block Diagram
Micron NAND Flash and LPDDR2 components
RoHS-compliant, “green” package
Separate NAND Flash and LPDDR2 interfaces
Space-saving multichip package (MCP)
Low-voltage operation (1.70–1.95V)
Industrial temperature range: –40°C to +85°C
NAND Flash
Device
NAND Flash
Power
NAND Flash
Interface
NAND Flash-Specific Features
Organization
• Page size
– x8: 2112 bytes (2048 + 64 bytes)
– x16: 1056 words (1024 + 32 words)
• Block size: 64 pages (128K + 4K bytes)
LPDRAM Power
LPDDR2-Specific Features
•
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Ultra-low-voltage 1.2V core power supply
1.2V HSUL-compatible inputs
Programmable read and write latencies
Programmable burst lengths: 4, 8, or 16
Partial-array self refresh (PASR)
Deep power-down (DPD) mode
Selectable output drive strength
Adjustable clock frequency and clock stop capabilities
Options
• LPDDR2
– 400 MHz (LPDDR800)
Note:
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LPDRAM
Device
1
LPDRAM
Interface
Marking
-25
1. For part numbering and physical part markings, see Part Numbering Information
(page 2).
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
Micron Confidential and Proprietary
Preliminary
162-Ball NAND and LPDDR2 MCP
Part Numbering Information
Part Numbering Information
Micron NAND Flash and LPDRAM devices are available in different configurations and
densities.
Figure 2: 162-Ball Part Number Chart
MT 29RZ* 4C
2D
ZZ*
H
G
MM -25
Micron Technology
I
.42S
Die Revision Code
.42S
Product Family
29R = LPDDR2-S4 SDRAM + SLC NAND
Production Status
NAND Density
4 = 4Gb
Blank = Production
ES = Engineering sample
MS = Mechanical sample
NAND Width
Operating Temperature Range
C = x16
I = Industrial (–40° to +85°C)
LPDDR2 SDRAM Density
LPDDR2 SDRAM Speed Grade
2 = 1Gb
-25 = 400 MHz (LPDDR800)
LPDDR2 SDRAM Width
Package Codes
D = x32
MM = 162-Ball 11 x 13.5 x 1.0 VFBGA
SLC e·MMC Density
and Controller
Chip Count Code
G = 1 NAND Flash; 1 LPDRAM; 0 e·MMC
Operating Voltage Range
H = 1.8V NAND,
1.2V, 1.2V LPDDR2 SDRAM
*Z = a null character used as a placeholder.
Note:
1. Not all possible combinations are available. Contact factory for availability.
Table 1: Production Part Numbers
Part Number
NAND Product
MT29RZ4C2DZZHGMM-25 I.42S MT29F4G16ABBDAM60A3WC1
LPDDR2 Product
Physical Part Marking
MT42L64M32D1G69AWC1
JW570
Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the
top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron
part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To
view the location of the abbreviated mark on the device, refer to customer service note
CSN-11, “Product Mark/Label,” at www.micron.com/csn.
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Micron Confidential and Proprietary
Preliminary
162-Ball NAND and LPDDR2 MCP
MCP General Description
MCP General Description
Micron all-in-one (AiO) MCP products combine NAND Flash and Mobile LPDRAM devices in a single MCP. These products target mobile applications with low-power, highperformance, and minimal package-footprint design requirements. The NAND Flash
and Mobile LPDRAM devices are also members of the Micron discrete memory products portfolio.
The NAND Flash and Mobile LPDRAM devices are packaged with separate interfaces
(no shared address, control, data, or power balls). This bus architecture supports an optimized interface to processors with separate NAND Flash and Mobile LPDRAM buses.
The NAND Flash and Mobile LPDRAM devices have separate core power connections
and share a common ground (that is, V SS is tied together on the three devices).
The bus architecture of this device also supports separate NAND Flash and Mobile
LPDRAM functionality without concern for device interaction. Operational characteristics for the NAND Flash and Mobile LPDRAM devices are found in the standard Micron
data sheets for each of the discrete devices.
For device specifications and complete Micron NAND Flash features documentation,
refer to the component data sheet at www.micron.com/nand, or contact your local Micron sales office.
For device specifications and complete Mobile LPDRAM features documentation, refer
to the component data sheet at www.micron.com/products/mobiledram, or contact
your local Micron sales office.
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© 2010 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Preliminary
162-Ball NAND and LPDDR2 MCP
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 3: 162-Ball FBGA (NAND x16; LPDDR2 x32) Ball Assignments
1
2
3
4
5
6
7
8
9
10
A
DNU
DNU
WP#
CLE
VCC
IO4
IO7
VCC
DNU
DNU
A
B
DNU
VCC
IO11
ALE
RE#
IO5
IO14
IO15
VSS
DNU
B
C
IO10
IO1
IO3
WE#
R/B#
IO6
C
D
IO8
IO0
IO2
CE#
IO12
IO13
D
E
VSS
IO9
NC
VDD2
VDD1
DQ31
DQ29
DQ26
DNU
E
F
VDD1
VSS
ZQ1
VSS
VSSQ
VDDQ
DQ25
VSSQ
VDDQ
F
G
VSS
VDD2
ZQ0
VDDQ
DQ30
DQ27
DQS3 DQS3# VSSQ
G
H
VSSCA
CA9
CA8
DQ28
DQ24
DM3
DQ15
J
VDDCA
CA6
CA7
VSSQ
DQ11 DQ13
K
VDD2
CA5
VREFCA
L
VDDCA
VSS
CK#
DM1
VDDQ
M
VSSCA
NC
CK
VSSQ
VDDQ
N
CKE0
CKE1
RFU
DM0
VDDQ
P
CS0#
CS1#
RFU
R
CA4
CA3
CA2
VSSQ
CA1
T
VSSCA VDDCA
DQS1# DQS1
DQS0# DQS0
DQ10
VDDQ
VSSQ
H
DQ14 DQ12
VDDQ
J
DQ9
VSSQ
K
DQ8
L
VDD2
VSS
VREFDQ
M
N
DQ5
DQ6
DQ7
VSSQ
P
DQ4
DQ2
DQ1
DQ3
VDDQ
R
DQ19
DQ23
DM2
DQ0
VDDQ
VSSQ
T
DQ17 DQ20
DQS2 DQS2# VSSQ
U
U
VSS
VDD2
CA0
VDDQ
V
VDD1
VSS
NC
VSS
VSSQ
VDDQ
DQ22
VSSQ
VDDQ
V
W
DNU
NC
NC
VDD2
VDD1
DQ16
DQ18
DQ21
DNU
W
Y
DNU
DNU
DNU
DNU
Y
1
2
9
10
3
4
5
6
7
8
Top View (ball down)
NAND
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LPDDR2
4
Supply
Ground
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Preliminary
162-Ball NAND and LPDDR2 MCP
Ball Assignments and Descriptions
Table 2: x16 NAND Ball Descriptions
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Symbol
Type
ALE
Input
Address latch enable: When ALE is HIGH, addresses can be
transferred to the on-chip address register.
Description
CE#
Input
Chip enable: Gates transfers between the host system and
the NAND device.
CLE
Input
Command latch enable: When CLE is HIGH, commands can be
transferred to the on-chip command register.
LOCK
Input
When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable BLOCK LOCK, connect LOCK to VSS
during power-up, or leave it unconnected (internal pulldown).
RE#
Input
Read enable: Gates information from the NAND device to the
host system.
WE#
Input
Write enable: Gates information from the host system to the
NAND device.
WP#
Input
Write protect: Driving WP# LOW blocks ERASE and
PROGRAM operations.
I/O[15:0]
Input/
output
Data inputs/outputs: The bidirectional I/Os transfer address,
data, and instruction information. Data is output only during
READ operations; at other times the I/Os are inputs.
R/B#
Output Ready/busy: Open-drain, active-LOW output that indicates
when an internal operation is in progress.
VCC
Supply
VCC: NAND power supply.
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© 2010 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Preliminary
162-Ball NAND and LPDDR2 MCP
Ball Assignments and Descriptions
Table 3: x32 LPDDR2 Ball Descriptions
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162ball_nand_lpddr2_j4xx_.pdf – Rev. B 11/11 EN
Symbol
Type
Description
CA[9:0]
Input
Command/address inputs: Provide the command and address
inputs according to the command truth table.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All CA inputs
are sampled on both the positive and negative edge of CK.
CS and CKE inputs are sampled at the positive edge of CK. AC
timings are referenced to clock.
CKE0, CKE1
Input
Clock enable.
CKE0 is used for a single LPDDR2 MCP product.
CKE1 is used for dual LPDDR2 MCP.
CS0#, CS1#
Input
Chip select:
CS0# is used for a single LPDDR2 MCP.
CS1# is used for a dual LPDDR2 MCP.
DM[3:0]
Input
Data mask:DM is an input mask signal for write data. Although DM balls are input-only, the DM loading is designed
to match that of DQ and DQS balls. DM[3:0] is DM for each of
the four data bytes, respectively.
For x16, unused DM balls become NC.
DQ[31:0]
Input/
output
Data bus: Data inputs/outputs.
DQ[31:16] are NC for x16 devices.
DQS[3:0]
DQS#[3:0]
Input/
output
Data strobe: Coordinates READ/WRITE transfers of data; one
DQS/DQS# pair per DQ byte.
VDD1
Supply
VDD1: LPDDR2 power supply 1.
VDD2
Supply
VDD2: LPDDR2 power supply 2.
VDDCA
Supply
VDDCA: LPDDR2 CA power supply.
VDDQ
Supply
VDDQ: LPDDR2 I/O power supply.
VREFCA
Supply
VREFCA: LPDDR2 reference for CA pins.
VREFDQ
Supply
VREFDQ: LPDDR2 reference for DQ pins.
VSSCA
Supply
VSSCA: LPDDR2 I/O ground.
VSSQ
Supply
VSSQ: LPDDR2 I/O ground.
ZQ, ZQ0, ZQ1
Input
External impedance (240-Ohm): This signal is used to calibrate the device output impedance.
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Preliminary
162-Ball NAND and LPDDR2 MCP
Ball Assignments and Descriptions
Table 4: Non-Device-Specific Descriptions
Note:
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Symbol
Type
VSS
Supply
Description
Symbol
Type
DNU
–
Do not use: Must be grounded or left floating.
NC
–
No connect: Not internally connected.
RFU1
–
Reserved for future use.
VSS: Shared ground.
Description
1. Balls marked RFU may or may not be connected internally. These balls should not be
used. Contact factory for details.
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Preliminary
162-Ball NAND and LPDDR2 MCP
Electrical Specifications
Electrical Specifications
Table 5: Absolute Maximum Ratings
Parameters/Conditions
Symbol
Min
Max
Unit
VCC and VDD1
supply voltage relative to VSS
VCC, VDD1
–0.4
2.3
V
VDD2
–0.4
1.8
V
VDDCA, VDDQ
–0.4
1.6
V
VIN
–0.4
1.6 or (VDDQ + 0.3),
whichever is less
V
–
–55
+125
°C
VDD2 supply voltage
relative to VSS
VDDCA and VDDQ supply voltage
relative to VSS
Voltage on any pin
relative to VSS
Storage temperature range
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 6: Recommended Operating Conditions
Parameters
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
1.70
1.80
1.95
V
Supply voltage
VDD1
1.70
1.80
1.95
V
Supply voltage
VDD2
1.14
1.20
1.30
V
VDDCA/ VDDQ
1.14
1.20
1.30
V
–
–25
–
+85
°C
I/O supply voltage
Operating temperature range
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Micron Confidential and Proprietary
Preliminary
162-Ball NAND and LPDDR2 MCP
Device Diagrams
Device Diagrams
Figure 4: 162-Ball (Single LPDDR2) Functional Block Diagram
VDD1
CS#0
VDD2
CKE0
VDDQ
LPDDR2
VDDCA
CK
CK#
VSS
DM
VSSQ
DQ
VSSCA
DQS/DQS#
VREFDQ
CA0-9
VREFCA
ZQ0
RZQ
CE#
CLE
VCC
ALE
VSS
RE#
NAND Flash
WE#
I/O
WP#
R/B#
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Micron Confidential and Proprietary
Preliminary
162-Ball NAND and LPDDR2 MCP
Device Diagrams
Figure 5: 162-Ball (Dual LPDDR2) Functional Block Diagram
CS0#
CS1#
CKE0
CKE1
CK
CK#
DM
DQ
DQS/DQS#
CA0-9
VDD1
LPDDR2
LPDDR2
VDD2
Die 0
Die 1
VDDQ
VDDCA
VSS
VSSQ
VSSCA
VREF
ZQ0
ZQ1
RZQ0
RZQ1
CE#
CLE
ALE
RE#
VCC
NAND Flash
VSS
WE#
WP#
I/O
R/B#
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Micron Confidential and Proprietary
Preliminary
162-Ball NAND and LPDDR2 MCP
Package Dimensions
Package Dimensions
Figure 6: 162-Ball FBGA (Package Code: MM)
Seating
plane
0.63 ±0.05
A
0.08 A
162X Ø0.36
Solder ball material
with Cu OSP ball pad:
LF35 (98.25% Sn, 1.2% Ag,
0.5% Cu, 0.05% Ni).
Dimensions apply to solder
balls post-reflow on Ø0.30
SMD ball pads.
Ball A1 ID
Ball A1 ID
10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
12.35 CTR
0.65 TYP
13.5 ±0.1
0.65 TYP
1.0 MAX
5.85 CTR
0.22 MIN
11 ±0.1
Note:
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1. All dimensions are in millimeters.
11
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© 2010 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Preliminary
162-Ball NAND and LPDDR2 MCP
Revision History
Revision History
Rev. B, Preliminary – 11/11
• Corrected ballout labeling sequence from ...VWX to ...VWY.
Rev. A, Preliminary – 02/10
• Initial release.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.