Transcript ALICE TRD Trigger

CBM
Common FrontEnd Electronics
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Introduction
µE technology choice
Overall Architecture
Preamplifier
Analog Memory
ADC
Clock and Time (re)generation
CNET Architecture
Volker Lindenstruth (www.ti.uni-hd.de)
Volker Lindenstruth
Kirchhoff Institute for Physics
Chair of Computer Science
University Heidelberg, Germany
Phone: +49 6221 54 9800
Fax:
+49 6221 54 9809
Email:
[email protected]
WWW: www.ti.uni-hd.de
The CBM Experiment
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Radiation hard Silicon (pixel/strip) Tracking System in a magnetic dipole field
Electron detectors: RICH & TRD & ECAL: pion suppression better 104
Hadron identification: TOF-RPC
Measurement of photons, π0, η, and muons: electromagn. calorimeter (ECAL)
High speed data acquisition and trigger system
Volker Lindenstruth (www.ti.uni-hd.de)
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Key Challenges
Remember: no trigger systen – FEE has to implement that on a per channel basis
• Global coherent clock/time distribution ~1ns
• Low-cost data readout
• Hit detection/selection (CNET) next neighbor
communication
• Common front-end electronics
• (very high rate) readout for vertex detector
• Generic Preamplifiers – modular amplifiers??
Volker Lindenstruth (www.ti.uni-hd.de)
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Making Chips ….
Volker Lindenstruth (www.ti.uni-hd.de)
A. Marchioro (CERN) 4
TRAP3
reticle
OASE-1
ATOLL
TRAP
UMC 180nm, 8“
Volker Lindenstruth (www.ti.uni-hd.de)
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Overall Electronics Requirements
• Three Categories
– Silicon Tracker
» Radiation tolerance 60 MRAD
» Time resolution <10 ns (we may have to accept pile-up)
» Channel count 2M (ITS) ~1M (STS)
» Channel area (25 µm)2
– Time of Flight System
» Radiation tolerance ~100 kRAD
» Time resolution 25 ps
» Channel count 60k
» Channel area (50 mm)2
– TRD, RICH, ECAL
» Radiation tolerance ~100 kRAD
» Time resolution <10 ns
» Channel count (>600k, 120k, 23k)
» Channel area [cm2] (1, 0.4, 10)
• One solution ??? – maybe two or three ???
Volker Lindenstruth (www.ti.uni-hd.de)
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Common Front-End Electronics
pre
Filter
PreAmp
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Si Strip
Pad
GEM's
PMT
APD's
AntiAliasing
Filter
Detector specific
Volker Lindenstruth (www.ti.uni-hd.de)
ADC
digital
Filter
Sample rate:
10-100 MHz
Dyn. range:
8...>12 bit
'Shaping'
1/t Tail
cancellation
Baseline
restorer
Hit
Finder
Hit
parameter
estimators:
Amplitude
Time
Backend
& Driver
Clustering
Buffering
Link protocol
generic
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Technology Considerations
• Radiation Hardness
– Not an issue for DSM – Vertex Detector may be an exception
• Speed
– Not a critical issue for CBM
• Routing
– Experience with existing designs show that 6 routing layers are typically
sufficient
• Power
– Reduces for smaller process sizes, current does not
• Cost
– Factor 2 cost for MPW and Engineering run between 180 and 130 nm
• Existing Expertise, IP
– Huge amount of existing IP cells and analog designs with appropriate experience
with the process available
• Conclusion
– Use UMC 180nm process as baseline process until critical issues require
technology migration
Volker Lindenstruth (www.ti.uni-hd.de)
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Over All Architecture
to/from next
neighbor hit
detection
N PreAmplifier
Blocks
Hit Detector
• Leading Edge
• peak
•…
Programmable
Finite State
Machine
DAC
send
Fast
Readout
DATA-out
start
Ain
Digital
Pipeline
Hit TDC
TIMER
stop
CLOCK
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1..N
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RE
sample
ADC
ANALOG
FIFO
Analog
Filter
to/from next
neighbor hit
detection
Volker Lindenstruth (www.ti.uni-hd.de)
Event
Buffers
Digital
Filters
different combinations
• sampling rate
• resoluion
• power
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The TAC Core
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Digital delay chain
Distributed RC-Network
Voltage on Cout increases linear with time
Holger Flemming, GSI, DVEE
CBM Meeting ,FEE 11.03.2005
Various other approaches suggested also (DLL, ....)
Preamplifier
Volker Lindenstruth (www.ti.uni-hd.de)
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Preamplifier (ADC interface)
Volker Lindenstruth (www.ti.uni-hd.de)
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Analog Memory
Data lifetime @ 10 Bits [# of samples]
Switched capacitor analog memory
Switched current analog memory
Temperature [deg C]
Volker Lindenstruth (www.ti.uni-hd.de)
David Muthers, Kaiserslautern 13
Common ADC
Volker Lindenstruth (www.ti.uni-hd.de)
David Muthers, Kaiserslautern 14
Common ADC
Volker Lindenstruth (www.ti.uni-hd.de)
David Muthers, Kaiserslautern 15
ADC Considerations
• PreAmp for 12 bit resolution = 72 dB SNR and THD
72 dB loop gain + 34 dB closed loop gain = 106 dB @ fT= 40 MHz
• 1 LSB = 245 µV  310 e @ Cfb = 200fF
• Thermal noise of feedback R / C @ Cfb=200fF = 150 µV (kT/C)
• Input referred noise of PreAmp is amplified by
A = 1+ Cfb/ Cshunt = ~100 ( 40dB)
 150 µV / 100 = 1.5 µV !!! (including pick up)
• Differential input helps to reduce pick up of noise irradiation
• PreAmp should be attached very close to detector PAD in order to
reduce Cshunt
• Pulse shaping by zero of PreAmp transfer function reduces
required dynamic range and hence saves power
• High order lowpass (Gm/C) filter is natural companion of ADconverter/digital chip
• Jitter Constraints on digitization clock (@12-Bit, 40 MSPS, 20 MHz
input): 12 ps for 0.3 LSB max. quantization error
Volker Lindenstruth (www.ti.uni-hd.de)
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2.5 GBit/sec SERDES @ UMC 180nm
• TX works (c.f. eye pattern)
• Clock generation 13.7 ps jitter
• Serializer power (sim) 180 mW
• RX being tested
Sitt Tontisirin,
Kaiserslautern
Volker
Lindenstruth (www.ti.uni-hd.de)
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SerDes / Clock Recovery
parallel
interface
input
8B/10B
encoder
serilaizer
preequalization
laser driver
with PhDet
laser driver
control &
debug
interface
parallel
interface
output
8B/10B
decoder
Volker Lindenstruth (www.ti.uni-hd.de)
control &
status
registers
deserilaizer
clock & data
recovery
to VCSEL
on-chip
to VCSEL
off-chip
CML
Output
to optical
transceiver
CML
input
from optical
transceiver
transimpedance
Amplifier &
limiting amplifier
from PIN
diode
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BuTiS – Bunchphase-Timing-System
Optical
Receiver
(Detector)
Pilot Delay
Control
MPX
Stream
with
Pilot
Signal
Laser
Diode/Modulato
r
Echoed
stream
propagatio
n delay
Variable
Optical
Delay
The optical delay is by nature
broadband, covering a whole
waveband (1310 or 1550nm)
Volker Lindenstruth (www.ti.uni-hd.de)
3-Port Circulator
A broadband propagation delay stabilization scheme
Forward
stream
propagatio
n delay
Optical
Receiver
(Detector)
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BuTis Summary
• Use of broadband optical RF-links and single mode fibers are
• mandatory, most components can be purchased from stock
• The fiber properties need careful attention to reach
100ps@1km
• A „BuTiS“- like system will surely be needed for FAIR
accelerators
• BuTiS has „campus-wide“ capabilities for realtime
synchronisation and timing
• At present conceptual design stage, system modifications
can be realized without costly modifications
• It can be build with moderate costs at the beginning, and later
extended to a very sophisticated topology
Volker Lindenstruth (www.ti.uni-hd.de)
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Clock and Timing distribution
10
D10
clk
Ctl
clr
10
2
n
2
Serializer
Deserializer
t0gen
t0dec
n
D10
clk
Ctl
clr
Δt = const ±δ = 0.8ns
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Volker Lindenstruth (www.ti.uni-hd.de)
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Fiber optics have become a commodity
High speed readout serial anyway
Use of glas as media simplifies grounding
Half- and full diplex almost same price
DCS functionality requires negligible
fraction of downlink
Use available uplink and fraction of
downlink for DCS network (and others)
Multi gigabit deserializers require very
stable, low jitter clock recovery
Why not use serial infrastructure also for
clock and time distribution
 advanced optical serializer/deserializer
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OASE
Volker Lindenstruth (www.ti.uni-hd.de)
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CNET System Level
Volker Lindenstruth (www.ti.uni-hd.de)
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CNET Link Protocol (some ideas)
Acronym Prio. Length Function
DATA
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32...272 data readout
DCS
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32...272 DCS
RdTrgV
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32...64 hit trigger
RdTrgC
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hit trigger
RdTrgB
4
16
hit trigger
T0
2
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Tnet
RESET
1
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DCS
IDLE
x
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Cnet
StdBy
N/A
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Cnet
Volker Lindenstruth (www.ti.uni-hd.de)
Description
downstream payload data format detector specific
DCS Payload, stripped by merger FPGA
next neighbor readout trigger command
downstream next neighbor readout trigger command
upstream next neighbor readout trigger broadcast command
upstream time counter reset
RESET command
idle message
link powered down message
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Ternary CAM Cell
• Save ~20% of area by optimized design:
–store 1/0 for a 1
–store 0/1 for a 0
–store 0/0 for don’t care (cell does not participate in match calculation)
• Cell size is 10.82 µm x 2.69 µm
write
match
power down
Volker Lindenstruth (www.ti.uni-hd.de)
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Power Regulators Issues
• FEE is operated in magnetic and ionizing areas
• FEE power requirements continue to move to lower
voltages <1V and high currents (Amperes)
• Copper significant cost and material factor
• Distributing LV from outside the detector requires
traveling long distances
• Regulators required on detector close to electronics
• LV power distribution in TRD requires about the same
power as entire electronics (part goes in to voltage drop
in copper and part into regulators on detector)
• There are no good low drop, high current voltage
regulators
Volker Lindenstruth (www.ti.uni-hd.de)
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Power Regulators Requirements
• Step Down regulator from moderately filtered external DC supply
(e.g. 40V)
• Tolerance against radiation (not radiation hard)
• Tolerance against magnetic fields
– Feasibility of a transformer with compensation coils for magnetic field
– Transformator saturation can be measured and compensated for automatically
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Very low noise (output and generated in environment)
Small outline
High efficiency
Run at high frequency (100 MHz?) for better filtering later and for
staying away from most relevant analog frequency domains
• Implement digital sequencers to generate externally triggered power
profiles (proactive regulation)
• Small sequencer chip plus external power transistor
• Lets start this project as Ph.D. thesis and not miss the boat again.
Volker Lindenstruth (www.ti.uni-hd.de)
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Over All Architecture
to/from next
neighbor hit
detection
N PreAmplifier
Blocks
Hit Detector
• Leading Edge
• peak
•…
Programmable
Finite State
Machine
DAC
send
Fast
Readout
DATA-out
start
Ain
Digital
Pipeline
Hit TDC
TIMER
stop
CLOCK
we
1..N
WE
.
.
.
RE
sample
ADC
ANALOG
FIFO
Analog
Filter
Event
Buffers
Digital
Filters
different combinations
• sampling rate
• resoluion
• power
Need global, synchronous time reference
to/from next
neighbor hit
detection
Volker Lindenstruth (www.ti.uni-hd.de)
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Summary
• CBM defines a new set of challenges in front-end
electronics
• Many key issues identified, many left for
additional work
• One baseline technology, common interfaces
and tooling to save cost and effort
Volker Lindenstruth (www.ti.uni-hd.de)
Note: slides were compiled from various sources
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and may not allways cite authors correctly
Thank You
Volker Lindenstruth (www.ti.uni-hd.de)
Volker Lindenstruth (www.ti.uni-hd.de)
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Low Jitter Clock Recovery (Tontisirin)
Volker Lindenstruth (www.ti.uni-hd.de)
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Open Questions
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Open questions concerning both, TAC and DLL solution
• TDC resolution required?
• Single / double hit resolution?
• Double hit only flagged?
• Integration Level (Geometry)?
• Event rate to cope with (100 kHz)?
• Discriminator specs (time over threshold)?
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min. and max. signal length
double hit resolution
Temperature?
Radiationhardness?
Interfaces?
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Discriminators, clock distribution, DAQ
Holger Flemming, GSI, DVEE
CBM Meeting ,FEE 11.03.2005
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New chip TC3 with lager devices, PMOS pair,…
 All MOS wider, but still minimum length for speed! This is bad for matching…
 Detail of VCO (Ringoscillator):
current sources under
wide power busses
VCO inverter
‘small’ inverter
interconnect
between VCO stages
(in light blue…)
loads under wide
power busses
P. Fischer, TI, Uni Mannheim, Seite 34
Summary
 Differential logic with diode-clamp load works (also at high speed). (This may not be the best solution!)
 Timer with ring oscillator, buffers, latches,… works
 PLL locks
 Matching is a big issue.
 Observed mismatch cannot be reproduced by Monte Carlo Simulations.
 Consequences: Submit matching test structures, or try out sizing…
 Time bin width of 150 ps achieved at 100µA in 0.35µm
 This leads to a single channel resolution (after correction of bin width) of s = 55ps, including mismatch
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Expected improvement by going to 0.18µm is at least a factor of 2 (at same current, large devices)
Another factor of two by increasing current.
Can probably use a bit shorter MOS than in simulation..
In total, s = 15ps seams possible in 0.18µm with no further tricks.
 Most of the presented work has been done by Michael Ritzert
P. Fischer, TI, Uni Mannheim, Seite 35
Status & Plans
 Layouts of crucial (dense) blocks is done: CAM cells, Flipflops, row decoder (F. Giesen’s Diploma Thesis)
 Most simulations (typical parameters) are done.
Speed is >500MHz for a CAM with 512 rows (parasitics of busses included)
 We plan to submit an 512 x 18 bit block (testing maximum speed needs full size!).
Layout area of this core will be 0.3mm x 1.4mm
 Testing will be done by setting all input bits & reading all output bits with shift registers.
Timing will be generated by several external fast strobe signals.
This stuff will be synthesized (with help from Rechnerarchitektur)
 We are confident to be ready until April 24.
: done
: missing
P. Fischer, TI, Uni Mannheim, Seite 36
Submission Plans
• Boundary condition 5x5 mm2
ADC Test structures (Muthers)
PLL structures (Tontisirin)
Full Custom CAM
Test Structures
DAC
Ring Oscillator
Peter Fischer
FC CAM
Fischer
Volker Lindenstruth (www.ti.uni-hd.de)
• Boundary condition 1.5x1.5 mm2
TsT
PeFi
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Summary
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First CBM FEE Meeting
Technology Baseline Choice UMC 180nm
Many existing building blocks and developments
Several key issues/items identified:
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Preamplifier
ADC
Clock Recovery (good enough for ToF?)
Serializer
• Integration with BuTis
• Two MPW submissions foreseeable
– April 5x5 mm2 some space left
– June MiniASIC 1.5x1.5 mm2
• We need a FEE recess soon to discuss many of the
outstanding preamplifier issues
Volker Lindenstruth (www.ti.uni-hd.de)
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Volker Lindenstruth (www.ti.uni-hd.de)
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