Transcript System Validation and Test Course

REASON Tutorial
Tomsk, Irkutsk, Vladivostok – September 6 -15, 2004
Hierarchical Defect-Oriented
Test Generation
Raimund Ubar
Tallinn Technical University
D&T Laboratory
Estonia
1
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Abstract
•
•
How to improve the testing quality at increasing complexities of today's
systems?
Two main trends: defect-oriented test and high-level modelling
– Both are caused by the increasing complexities of systems based on deepsubmicron technologies
•
•
•
•
•
The complexity problems in testing digital systems are handled by raising
the abstraction levels from gate to register-transfer level (RTL)
instruction set architecture (ISA) or behavioral levels
To handle defects in circuits implemented in deep-submicron
technologies, new fault models and defect-oriented test methods should
be used
Trends to high-level modelling and defect-orientation are opposite
As a promising compromise and solution is: to combine hierarchical
approach with defect orientation
Decision Diagrams serve as a good tool for hierarchical modelling of
defects in digital systems
2
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Outline
• Introduction to Digital Test (3)
• How to improve test quality at increasing complexity of
systems (11)
• High-level modelling and defect-orientation (6)
• Decision Diagrams - beyond BDDs (8)
• Hierarchical test generation (11)
– General concepts
– Test generation for RT Level systems
– Test generation for Microprocessors
• Conclusions
3
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Introduction: the Problem is Money?
Cost of quality
Cost
Cost of
testing
Cost of
the fault
How to succeed?
Try too hard!
How to fail?
Try too hard!
(From American Wisdom)
Test
coverage
function
100%
Time
Conclusion:
Quality
0%
Optimum
test / quality
Copyright 2000-2003 by Raimund Ubar
100%
“The problem of testing
can only be contained
not solved”
T.Williams
Technical University Tallinn, ESTONIA
4
Introduction: How Much to Test?
Paradox:
Time can be your best friend
or your worst enemy
264 input patterns (!)
for 32-bit accumulator
will be not enough.
A short will change the circuit
into sequential one,
and you will need because of that
265 input patterns
(Ray Charles)
Y = F(x1, x2, x3)
Bridging fault
Paradox:
Mathematicians counted that Intel 8080
needed for exhaustive testing 37 (!) years
Manufacturer did it by 10 seconds
Majority of functions will never activated
during the lifetime of the system
y
x1
x2
x3
State q
0
1
*
&
&
1
Y = F(x1, x2, x3,q)
5
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Introduction: Hierarchy
Paradox:
The best place to start is
with a good title.
Then build
a song around it.
To generate a test
for a block in a system,
the computer
needed
2 days and 2 nights
An engineer
did it by hand
with 15 minutes
So, why
computers?
(Wisdom of country music)
Sea of gates
Sequence
of 216 bits
&
16 bit
counter
1
System
6
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Outline
• Introduction to Digital Test
• How to improve test quality at
increasing complexity of systems
• High-level modelling and defect-orientation
• Decision Diagrams (beyond BDDs)
• Hierarchical test generation
– General concepts
– Test generation for RT Level systems
– Test generation for Microprocessors
• Conclusions
7
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Complexity vs. Quality
Problems:
•
Traditional low-level test generation and fault simulation methods and
tools for digital systems have lost their importance because of the
complexity reasons
•
Traditional Stuck-at Fault (SAF) model does not quarantee the
for deep-submicron technologies
quality
New solutions:
•
The complexity can be reduced by raising the abstraction levels from
gate to RTL, ISA, and behavioral levels
– But this moves us even more away from the real life of defects (!)
•
To handle adequately defects in deep-submicron technologies, new fault
models and defect-oriented test generation methods should be used
– But, this is increasing even more the complexity (!)
•
To get out from the deadlock, these two opposite trends should be
combined into hierarchical
approaches
8
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Fault and defect modeling
Defects, errors and faults
•
•
•
•
An instance of an incorrect
operation of the system being
tested is referred to as an
error
The causes of the observed
errors may be design errors
or physical faults - defects
Physical faults do not allow a
direct mathematical treatment
of testing and diagnosis
The solution is to deal with
fault models
System
Defect
Component
Fault
Error
9
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Transistor Level Faults
Stuck-at-1
Broken (change of the function)
Bridging
Stuck-open  New State
Stuck-on (change of the function)
Short (change of the function)
Stuck-off (change of the function)
Stuck-at-0
SAF-model is not able to cover all the
transistor level defects
How to model transistor defects ?
10
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Mapping Transistor Faults to Logic Level
A transistor fault causes a change in a logic
function not representable by SAF model
Function:
y
x1
x4
y  x1 x2 x3  x4 x5
Faulty function:
y d  ( x1  x4 )(x2 x3  x5 )
Short
Defect variable:
x2
d=
0 – defect
d
is missing
1 – defect
d
is present
Generic function with defect:
y*  ( y  d )  ( y  d )
d
x3
x5
Mapping the physical defect onto the
logic level by solving the equation:
Copyright 2000-2003 by Raimund Ubar
y *
1
d
Technical University Tallinn, ESTONIA
11
Mapping Transistor Faults to Logic Level
Function:
y  x1 x2 x3  x4 x5
Faulty function:
y d  ( x1  x4 )(x2 x3  x5 )
Generic function with defect:
y
x1
x4
Short
Test calculation by Boolean derivative:

x2
x3
y*  ( y  d )  ( y  d )
d
x5

y *  ( x1 x2 x3  x4 x5 )d  ( x1  x4 )(x2 x3  x5 )d


d
d
 x1 x2 x4 x5  x1 x3 x4 x5  x1 x2 x3 x4 x5  1
12
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Generalization: Functional Fault Model
Constraints calculation:
Fault-free Faulty
y*  F * ( x1, x2 ,...,xn , d )  dF  dFd
d = 1, if the defect is present
Component with defect:
Wd
Component
F(x1,x2,…,xn)
Defect
Logical constraints
Constraints:
y
W
d
y *

1
d
Fault model:
(dy,Wd), (dy,{Wkd})
13
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Functional Fault Model for Stuck-ON
NOR gate
Stuck-on
VDD RN
VY 
( RP  RN )
VDD
x1
x2
RN
Y
x1
RP
x1
x2
y
yd
0
0
1
1
0
1
0
0
1
0
0
Z: VY
1
1
0
0
y*  d ( x1  x2 )  d ( x1 x2  x1 x2 Z ) 
 x1 x2  x1 x2 dZ
x2
VSS
Conducting path for “10”
Condition of the fault potential detecting:
W  y * / d  x1 x2 Z  1
d
14
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Functional Fault Model for Stuck-Open
Test sequence is
needed: 00,10
NOR gate
x1
x2
y
yd
Stuck-off (open)
0
0
1
1
0
1
0
0
t x1 x2 y
1
0
0
Y’
1
0
0
1
1
1
0
0
2
1
0
1
VDD
x1
x2
Y
x1
y*  d ( x1  x2 )  d ( x1 x2  x1 x2 y ' ) 
 x2 ( x1  dy' )
x2
VSS
No conducting path
from VDD to VSS for “10”
Copyright 2000-2003 by Raimund Ubar
W  y * / d  x1 x2 y'  1
d
15
Technical University Tallinn, ESTONIA
Functional Fault Model
Example:
xk
Bridging fault between leads xk and xl
xl
x*k
d
xk *  (d  xk )  (d  xk )  (d  xk )  (d  xk  xl )
xk*= f(xk,xl,d)
W d  xk * / d  xk  xl
Wired-AND
model
d
The condition
W d  xk xl  1
means that
in order to detect the short between leads xk and xl
on the lead xk
we have to assign to xk the value 1 and to xl the value 0.
16
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Functional Fault Model
Bridging fault causes a
feedback loop:
Example:
A short between leads xk and xl
changes the combinational circuit
into sequential one
x1
&
x2
Equivalent faulty circuit:
x1
W  y * / d  x1x2 x3 y'  1
d
Sequential constraints:
Copyright 2000-2003 by Raimund Ubar
t x1 x2 x 3 y
1 0
1 0
2 1 1 1 1
&
x3
y*  d ( x1 x2  x3 )  d ( x1 x2 y ' x3 ) 
x1 x2 (d  y ' ) x3
y
x2
&
&
&
y
x3
17
Technical University Tallinn, ESTONIA
First Step to Quality
How to improve the test quality at the increasing
complexity of systems?
Mapping
First step to solution:
Functional fault model
was introduced
as a means
for mapping physical defects
from the transistor or layout level
to the logic level
High
level
System
WFk
W Sk
Component
k
Low level
Bridging fault
Environment
Mapping
18
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Outline
• Introduction to Digital Test
• How to improve test quality at increasing complexity of
systems
• High-level modelling and defectorientation
• Decision Diagrams (beyond BDDs)
• Hierarchical test generation
– General concepts
– Test generation for RT Level systems
– Test generation for Microprocessors
• Conclusions
19
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Register Level Fault Models
RTL statement:
K: (If T,C) RD  F(RS1, RS2, … RSm),  N
Components (variables)
RT level faults:
of the statement:
K  K’ - label faults
K
- label
T  T’ - timing faults
T
- timing condition
C  C’ - logical condition faults
C
- logical condition
RD  RD - register decoding faults
RD
- destination register
RS  RS - data storage faults
RS
- source register
F  F’ - operation decoding faults
F
- operation (microoperation) 
- data transfer faults

- data transfer
N
- control faults
N
- jump to the next statement (F)  (F)’ - data manipulation faults
20
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Fault Models for High-Level Components
Decoder:
- instead of correct line, incorrect is activated
- in addition to correct line, additional line is activated
- no lines are activated
Multiplexer (n inputs log2 n control lines):
- stuck-at - 0 (1) on inputs
- another input (instead of, additional)
- value, followed by its complement
- value, followed by its complement on a line whose address differs in 1 bit
Memory fault models:
- one or more cells stuck-at - 0 (1)
- two or more cells coupled
21
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Fault models and Tests
Dedicated functional fault model for multiplexer:
– stuck-at-0 (1) on inputs,
– another input (instead of, additional)
– value, followed by its complement
Functional
fault model
– value, followed by its complement on a line whose address differs in
one bit
Test
description
22
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Faults and Test Generation Hierarchy
Functional
approach
F
Structural
approach
Test
Higher Level Module
System
W Fk
Fk
Test
Module
W F ki
F ki
Test
Gate
Copyright 2000-2003 by Raimund Ubar
WFki
W Sk
Network
of modules
W S ki
Network
of gates
W
d
ki
WSki
Component
Lower level
ki
Bridging fault
k
WF k
Environment
Interpretation of
WFk:
- as a test
on the lower level
- as a functional fault
on the higher level
Circuit
23
Technical University Tallinn, ESTONIA
Hierarchical Defect-Oriented Test Analysis
Functional
fault
detected
Functional fault activated
Defect
High-level
simulation
d

Physical
defect
analysis
yG


Module
Y
High-level
fault analysis
Complex gate
Gate-level
simulation
yM
BDDs
Gate-level
fault analysis
DDs
System
24
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Outline
• Introduction to Digital Test
• How to improve test quality at increasing complexity of
systems
• High-level modelling and defect-orientation
• Decision Diagrams (beyond BDDs)
• Hierarchical test generation
– General concepts
– Test generation for RT Level systems
– Test generation for Microprocessors
• Conclusions
25
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Binary Decision Diagrams
y
x1 1
0
x2
1
y  x1  x2 ( x3  x4 x5 )  x6 x7
x3
x4
Functional BDD
Simulation:
x5
x1 x2 x3 x4 x5 x6 x7
0 1 1 0 1 0 0
y 1
Boolean derivative:
x6
x7
y
 x1  x6 x7 x2 x4 x5  1
x3
0
26
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Elementary Binary Decision Diagrams
Elementary BDDs:
x1
x2 & y
x1
x3
OR
x1
x2 1 y
x1
x3
x2
AND
x2
x3
y
Copyright 2000-2003 by Raimund Ubar
x1
y
y
x1
Adder
x2
x3
x3
NOR
1
+
x2
x3
x1
x2
x3
x1
x2
x3
x2
x3
27
Technical University Tallinn, ESTONIA
Building a SSBDD for a Circuit
Structurally Synthesized BDDs:
DD-library:
Given circuit:
x1
x2
x21 1
a
&
x22
x3
y
a
b
a
x1
b
y
1
b
Compare to
x22
x21
x3
Superposition of DDs 
y
x22
a
Superposition of Boolean functions:
y  a & b  ( x1  x21 )(x22  x3 )
SSBDD
y
x3
b
x1
x22
x21
x3
a
28
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Representing by SSBDD a Circuit
Structurally synthesized BDD
for a subcircuit (macro)
71
4
5
6
73
1
Macro
1
2
3
y
&
7
&
&
d
&
72
&
e
b
&
73
5
1
a
2
y
71
72
c
&
6
0
y = cyey = cy  ey = x6,e,yx73,e,y  deybey
y = x6x73  ( x1  x2 x71) ( x5 x72)
To each node
of the SSBDD
a signal path in the circuit
corresponds
29
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Fault modeling on SSBDDs
The nodes represent signal paths through gates
Two possible faults of a DD-node represent all the stuck-at faults
along the signal path
Macro
1
2
71
3
4
5
&
7
&
&
6
a
&
72
&
73
1
e
b
&
73
y
d
y
5
1
c
&
6
2
71
72
123 4 5 6 7 y
Test pattern:
11
00 1 1
0
30
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
High-Level Decision Diagrams
Superposition of High-Level
DDs:
R2
y4
1
A single DD for a subcircuit
y1
y2
y3
a
R1 
M1
+
0
2
y4
IN

c
M3

0
y3
2
R2 
d
R2 + M3
Instead of simulating
all the components in the circuit,
only a single path in the DD should be traced
Copyright 2000-2003 by Raimund Ubar
y1
R1 + R2
IN + R2
IN
R1
3
*
M1
0
1
1
b
M2
R2
R2
e

#0
0
y2
R1 * R2
1
IN* R2
M2
Technical University Tallinn, ESTONIA
31
Fault Modeling on High Level DDs
High-level DDs (RT-level):
R2
0
y4
Terminal nodes represent:
1
RTL-statement faults:
data storage,
data transfer,
data manipulation faults
Nonterminal nodes
represent:
RTL-statement
faults:
label,
timing condition,
logical condition,
register decoding,
operation decoding,
control faults
Copyright 2000-2003 by Raimund Ubar
2
y2
y3
a
M1
+

M2
0
y3
*
1
2
e
M3

y4
c
b

IN
R2
0
y1
R1 + R2
1
y1
R1 
#0
d
R2 
3
IN + R 2
IN
R1
y2
0
R 1* R 2
1
IN* R 2
32
Technical University Tallinn, ESTONIA
Hierarchical Diagnostic Modeling
Two trends:
• high-level
modeling
– to cope
with
complexity
• low-level
modeling
– to cope
with
physical
defects,
to reach
higher
acuracy
Copyright 2000-2003 by Raimund Ubar
High-Level DD-s
BDD-s
Boolean differential algebra
Functional
fault
detected
Functional fault activated
Defect
High-level
simulation
d

Physical
defect
analysis
yG


Complex gate
yM
Y
High-level
fault analysis
Gate-level
simulation
Module
Gate-level
fault analysis
System
33
Technical University Tallinn, ESTONIA
Outline
• Introduction to Digital Test
• How to improve test quality at increasing complexity of
systems
• High-level modelling and defect-orientation
• Decision Diagrams (beyond BDDs)
• Hierarchical test generation
– General concepts
– Test generation for RT Level systems
– Test generation for Microprocessors
• Conclusions
34
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Hierarchical Test Generation
•
•
In high-level symbolic test generation the test properties of components
are often described in form of fault-propagation modes
These modes will usually contain:
– a list of control signals such that the data on input lines is reproduced
without logic transformation at the output lines - I-path, or
– a list of control signals that provide one-to-one mapping between data inputs
and data outputs -
F-path
•
The I-paths and F-paths constitute connections for propagating test
vectors from input ports (or any controllable points) to the inputs of the
Module Under Test (MUT) and to propagate the test response to an
output port (or any observable points)
•
In the hierarchical approach, top-down and bottom-up strategies
can be distinguished
35
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Hierarchical Test Generation Approaches
Bottom-up approach:
•
•
•
•
•
Pre-calculated tests for components
generated on low-level will be
assembled at a higher level
It fits well to the uniform
hierarchical approach to test, which
covers both component testing and
communication network testing
However, the bottom-up algorithms
ignore the incompleteness problem
The constraints imposed by other
modules and/or the network
structure may prevent the local test
solutions from being assembled
into a global test
The approach would work well only
if the the corresponding testability
demands were fulfilled
A
a
System
D
B
C
c
a,c,D
fixed
x - free
a
D
c
Module
A = ax
D: B = bx
C = cx
36
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Hierarchical Test Generation Approaches
Top-down approach:
•
•
•
Top-down approach has been
proposed to solve the test
generation problem by deriving
environmental constraints for
low-level solutions.
This method is more flexible
since it does not narrow the
search for the global test
solution to pregenerated patterns
for the system modules
However the method is of little
use when the system is still
under development in a top-down
fashion, or when “canned” local
tests for modules or cores have
to be applied
A
System
a’
D’
B
c’
C
a’,c’,D’
fixed
x - free
a’x
d’x
c’x
Module
A = a’x
D’ = d’x
C = c’x
37
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Hierarchical Test Generation on DDs
Hierarhical test generation with DDs: Scanning test (defect-oriented)
Single path activation in a single DD
Data function R1* R2 is tested
y1
y3
M1
+
M2
*
0
e
#0
1
2
M3

y4
c
b

IN
y2
a

R2
y4
Data path
R1 
Decision Diagram
R2
0
y3
0
y1
R1 + R2
1
R2 
1
2
d
3
Test program: Control: y1 y2 y3 y4 = x032
Data:
For all specified pairs of (R1, R2)
IN + R2
IN
R1
y2
0
R1 * R2
1
IN* R2
Low level test data (constraints W)
Copyright 2000-2003 by Raimund Ubar
38
Technical University Tallinn, ESTONIA
Test Generation on High Level DDs
High-level test generation with DDs: Conformity test (High-level faults)
Multiple paths activation in a single DD
Control function y3 is tested
Decision Diagram
R2
y4
Data path
1
y1
y3
M1
+

M2
y4
2
#0
R2
0
y3
e
R2 
1
2
*
R1 + R2
1
M3

0
y1
c
b

IN
y2
a
R1 
0
d
3
IN + R2
IN
R1
y2
0
R1 * R2
1
IN* R2
Test program: Control: For D = 0,1,2,3: y1 y2 y3 y4 = 00D2
Activating high-level faults: Data: Solution of R1+ R2  IN  R1  R1* R2
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
39
Defect-Oriented Test Generation
Test generation for a bridging fault:
Component
F(x1,x2,…,xn)
Bridge between leads 73 and 6
1
2
1
3
&
4
7
72
&
73
0
a
D
&
1
5
6
D
71
1
Wd
Macro
d
&
&
D
1
&
Fault manifestation:
e
D
&
y
Wd = x6x7= 1: x6 = 0, x7 = 1,
D
x7 = D
1
Fault propagation:
y
W d  ( x6  x7 ,3 )(x5  x7 , 2 ) x1 x2 ( x6 x7 ) 
x7 ,1
 x1 x2 x5 x6 x7  1
a path
Defect
b
c
y Activate
Wd
x2 = 1, x1 = 1, b = 1, c = 1
Line justification:
b = 1: x5 = 0
40
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Test Generation with SSBDDs
Defect Wd manifestation:
1
2
71
3
4
5
(dx7,Wd)
&
7
&
&
Macro
Wd = x6x7= 1: x6 = 0, x7 = 1, x7 = D
Functional Fault dx7 propagation:
e
x1 = 1, x2 = 1, x5 = 0
d
a
&
72
b
&
&
73
y
y
6
c
&
73
6
No fault:
dx7 =0: x7=1
5
1
1
Bridge between leads 7 and 6: (dx7,Wd)
Test pattern for the node 71
the constraint
x6x7= 1:
at
2
71
Wd =
123 4 5 6 7 y
11
Copyright 2000-2003 by Raimund Ubar
00 1 1
0
72
Defect:
dx7 =1: x7=0
Technical University Tallinn, ESTONIA
41
Test Generation for Microprocessors
High-Level DDs for a microprocessor (example):
DD-model of the
microprocessor:
Instruction
set:
I1 :
I2 :
I3 :
I4 :
I5 :
I6 :
I7 :
I8:
I9 :
I10:
MVI A,D
MOV R,A
MOV M,R
MOV M,A
MOV R,M
MOV A,M
ADD R
ORA R
ANA R
CMA A,D
A  IN
RA
OUT  R
OUT  A
R  IN
A  IN
AA+R
AAR
AAR
AA
A
3
OUT
I
R
4
I
1,6
IN
2,3,4,5
7
A
R
2
I
5
A+R
8
AR
9
AR
10
A
A
IN
A
1,3,4,6-10
R
42
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Test Generation for Microprocessors
High-Level DD-based structure of the microprocessor (example):
DD-model of the
microprocessor:
IN
A
3
R
OUT
I
R
4
I
1,6
IN
2,3,4,5
7
A
OUT
R
A
I
2
I
5
A+R
8
AR
9
AR
10
A
A
IN
A
1,3,4,6-10
R
43
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Test Generation for Microprocessors
Scanning test program for adder:
DD-model of the
microprocessor:
A
OUT
3
I
R
4
I
1,6
A
R
I
8
A
9
5
IN
1,3,4,6-10
R
IN
2,3,4,5
7
2
Instruction sequence T = I5 (R)I1 (A)I7 I4
for all needed pairs of (A,R)
10
A
OUT
I4
A
I7
A+R
A
I1
AR
R
IN(2)
AR
A
I5
R
Time:
IN(1)
t
t-1
Observation
Test
t-2
t-3
Load
44
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Test Generation for Microprocessors
Conformity test program for decoder:
DD-model of the
microprocessor:
Instruction sequence
A
OUT
3
I
R
4
I
1,6
7
A
R
2
I
5
8
A
IN
1,3,4,6-10
R
for all DI1 - I10 at given A,R,IN
IN
2,3,4,5
T = I5 I1 D I4
Data generation:
A
Data
A+R
AR
9
AR
10
A
Functions
IN
A
R
I1 , I6
I 2 , I 3 I4 , I5
I7
I8
I9
I10
IN
A
A+R
AR
AR
A
0
101
110
0
101
1011
111
0
0
Data IN,A,R are generated so that
the values of all functions were different
45
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
Conclusions
• Physical defects can be formally mapped to the
logical level by Boolean differential calculus
• Functional fault model is a universal means for
mapping test results from lower levels to higher
levels, giving a formal basis for hierarchical
approaches to test generation and fault simulation
• Decision diagrams is a suitable tool which can be
used successfully both, on the logic level, and also on
higher register transfer or behavioral levels
46
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
References
1.
2.
3.
4.
5.
6.
7.
8.
N.Jha, S.Gupta. Testing of Digital Systems. Cambridge University Press 2003, 1000
p.
S.Mourad, Y.Zorian. Principles of Testing Electronic Systems. J.Wiley & Sons, Inc.
New York, 2000, 420 p.
M.L.Bushnell, V.D.Agrawal. Essentials of Electronic testing. Kluwer Acad.
Publishers, 2000, 690 p.
M. Abramovici et. al. Digital Systems Testing & Testable Designs. Computer
Science Press, 1995, 653 p.
R.Ubar. Test Synthesis with Alternative Graphs. IEEE Design and Test of
Computers. Spring, 1996, pp.48-59.
J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using
Decision Diagram Representations. JETTA: Theory and Applications. Kluwer
Academic Publishers. Vol. 16, No. 3, pp. 213-226, 2000.
R.Ubar, W.Kuzmicz, W.Pleskacz, J.Raik. Defect-Oriented Fault Simulation and Test
Generation in Digital Circuits. ISQED’02, San Jose, California, March 26-28, 2001,
pp.365-371.
T.Cibáková, M.Fischerová, E.Gramatová, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar.
Hierarchical Test Generation with Real Defects Coverage. Pergamon Press. J. of
Microelectronics Reliability, Vol. 42, 2002, pp.1141-114.
47
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA
References
• European Projects:
– EEMCN, FUTEG, ATSEC, SYTIC, VILAB, REASON, eVIKINGS II
• Special thanks to:
– EU project IST-2000-30193 REASON
– Cooperation partners: IISAS Bratislava, TU Warsaw
– Colleagues: J.Raik, A.Jutman, E.Ivask, E.Orasson a.o. (TU Tallinn)
• Contact data:
–
–
–
–
–
–
Tallinn Technical University
Computer Engineering Department
Address: Raja tee 15, 12618 Tallinn, Estonia
Tel.: +372 620 2252, Fax: +372 620 2253
E-mail: [email protected]
www.ttu.ee/ˇraiub/
48
Copyright 2000-2003 by Raimund Ubar
Technical University Tallinn, ESTONIA