Transcript Design for Testability

DESIGN FOR TESTABILITY
Raimund Ubar
[email protected]
Technical University Tallinn, ESTONIA
Design for Testability
Lectures
• Testability of Digital Systems
• Design for Testability Methods
• BIST/BISD
Practical Works
• Two laboratory works
• Course work
Technical University Tallinn, ESTONIA
Literature
• L.-T.Wang, C.-W.Wu, X.Wen. VLSI Test Principles and
Architectures. Elsevier, 2006, 777 p.
• O.Novak, E.Gramatova, R.Ubar. Handbook of Testing Electronic
Systems. Czech TU Publishing House, 2005, 395 p.
• A.Miczo. Digital Logic Testing and Simulation. Wiley-Interscience,
New Yersey, 2003, 668 p.
• N.Jha, S.Gupta. Testing of Digital Systems. Cambridge Univ.
Press, 2003, 1000 p.
• R.Ubar, J.Raik, Th.Vierhaus. IGI Global, Hershey – New York,
2011, 550 p.
Technical University Tallinn, ESTONIA
Literature
Other:
• H.-J.Wunderlich, Ed. Models in Hardware Testing. Springer, 2010.
• M.Gössel, E.Sogomonjan et. al. New Methods of Concurrent
Checking. Springer, 2008.
• D.Gizopulos. Advances in Electronic Testing, Technology &
Engineering. Springer, 2006.
• D.Gizopulos, A.Paschalis, Y.Zorian. Embedded Processor-Based
Self-Test. Kluwer Acad. Publishers, 2004.
Technical University Tallinn, ESTONIA
Goals of the DFT Course
• To give the basic knowledge:
– How to improve test quality at
increasing complexities of systems?
• This knowledges includes
– understanding of how the physical
defects can influence on the behavior
of systems, and what is diagnostic
modelling
– understanding the meaning of
testability, and how to design well
testable systems
– learning the basic methods of making
systems self-testable
• The goal is also to give some hands-on
experience of solving test related
problems
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Practical Importance of testability?
• To improve the manufacturing
processes and to increase the yield
• To design reliable systems out of not
reliable components which leads to
the need of fault-tolerance
• Field diagnosis is the traditional task
• The Rule of Ten is the Sword of
Damokles
• The increasing complexity of VLSI
circuits has made test and diagnosis
the most complicated problems in
digital design
Automated diagnosis is
needed
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6
© Raimund Ubar
Integreeritud elektroonikasüsteemide ja biomeditsiinitehnika tippkeskus
Why the topic of DFT is important?
1. We depend too much on
computers and on the
technical systems controlled by
computers
 Tiina Ubar
7
Integreeritud elektroonikasüsteemide ja biomeditsiinitehnika tippkeskus
© Raimund Ubar
Computers and Embedded Systems
Embedded systems
98%
Universal
computers
2%
98 %
Microprocessor
market shares
We notice our dependency on
electronics only when it suddenly
gives up to work
8
Research in ATI
© Raimund Ubar
Why the topic of DFT is important?
2. Engineering has two sides:
- 99% of the engireering creation brings us happiness
- 1% causes trouble (the blame against engineers)
Engineering artifacts must be safe, secure and dependable
1991. Fault in the Patriot missile in the Gulf War killing 28 soldiers and injuring 100 people
1995. Intel Pentium processor was found faulty $475 millions of loss
1995. Ariane 5 reached the altitude of 3700 m and
exploded – $7 billions of loss
2003. Space Shuttle Columbia disaster killing all 7
crew members
2010. Failure in the Toyota’s anti-lock brake
system - 4,5 millions cars back to the industry
In 5 years the US
economic loss
from computer
bugs
has increased
5
times
Now 60 billions
USD per year
9
Introduction: Testing World
Test
experiment
(BIST)
System
Test
result
Fault simulation
Test
System
model
Fault diagnosis
Fault
dictionary
Go/No go
Located defect
Test generation
Test tools
Technical University Tallinn, ESTONIA
© Raimund Ubar
What is a test?
Testprogram
12 + 10 = ?
How many
test patterns
are needed
to test an adder?
Processor
Diagnosis
22
Test
results
11
Hierarchy: Divide and Conquer
Engineer vs. computer:
To generate a test
for a component
in a system,
the computer
needed
2 days and 2 nights
An engineer
did it „by hand“
with 15 minutes
So, why computers?
The best place to start is
with a good title.
Then build
a song around it.
(Wisdom of country music)
Sea of gates
Sequence
of 216 bits
&
16 bit
counter
1
System
Design for Testability
Technical University Tallinn, ESTONIA
Integreeritud elektroonikasüsteemide ja biomeditsiinitehnika tippkeskus
© Raimund Ubar
Why the topic of DFT is important?

The main property of
today’s systems is
COMPLEXITY

To manage the complexity
we have to know methods
like:

- abstraction

- modeling

- simulation

- hierarchical
„divide and conquer“

- ...
13
© Raimund Ubar
Why Design for Testability?
Test generation process for detecting a fault:
?
Know-how
011001
Defect
Expert systems
were used in Europe
but not in US
Expert system is needed to help the test programmer
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© Raimund Ubar
Why Design for Testability?
Test generation process for detecting a fault:
Defekt
?
Hard-to-testpart
New paradigm
ScanPath Design
011001
Gordion
Knot
011001
15
mindmappingsoftwareblog.com
© Raimund Ubar
Alexander cuts the Gordian Knot
Jean-Simon Berthélemy (1743–1811)
16
Making Systems Transparent
IN
OUT
Combinational
circuit
q’
R
q
theisleofwightcomputergeek.co.uk
IN
Combinational
circuit
OUT
Scan-IN
q’
R
q
Scan-Path design strategy
Scan-OUT
Technical University Tallinn, ESTONIA
17
Boundary Scan Standard
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Design for Testability
To ways for improving testability with inserting of control
points:
System
under
test
Improving
controllability
Improving
observability
Control points
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Introduction: Ad Hoc Design for Testability
Method of Test Points:
Block 1
Block 2
Block 1 is not observable,
Block 2 is not controllable
Improving controllability and observability:
OP
Block 1
1
CP
Block 1
Block 2
1- controllability:
CP = 0 - normal working mode
CP = 1 - controlling Block 2
with signal 1
Block 2
0- controllability:
CP = 1 - normal working mode
CP = 0 - controlling Block 2
with signal 0
OP
&
CP
Technical University Tallinn, ESTONIA
Introduction: Tradeoffs
Amusing testability:
Theorem:
Proof:
You can test an arbitrary digital system by only 3 test patterns
if you design it approprietly
011
&
101
011
101
011
001
&
001
010
&
101
1
001
?
&
011
101
&
001
Solution: System  FSM  Scan-Path  CC  NAND
Technical University Tallinn, ESTONIA
Introduction: Built-in Self-Test
Cores have to be tested on chip
Source: Elcoteq
Copyright 2010 Raimund Ubar
Source: Intel
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Introduction: Self-Test in Digital Systems
Test architecture components:
• Test pattern source & sink
• Test Access Mechanism
• Core test wrapper
SoC
SoC
SRAM
Test Access
Mechanism
Peripheral
Component
Interconnect
Wrapper
CPU
SRAM
ROM
Core
Under
Test
Source
Sink
Test Access
Mechanism
DRAM
MPEG
UDL
Solutions:
• Off-chip solution
– need for external ATE
• Combined solution
– mostly on-chip, ATE
needed for control
• On-chip solution
– BIST
Technical University Tallinn, ESTONIA
Self-Test in Complex Digital Systems
SoC
SoC
SRAM
Peripheral
Component
Interconnect
Wrapper
CPUSource
Core
Under
Test
SRAM
ROM
Sink
DRAM
MPEG
UDL
Test architecture components:
• Test pattern source & sink
• Test Access Mechanism
• Core test wrapper
Solutions:
• Off-chip solution
– need for external ATE
• Combined solution
– mostly on-chip, ATE
needed for control
• On-chip solution
– BIST
Technical University Tallinn, ESTONIA 24
Introduction: What is BIST
• On circuit
– Test pattern generation
Test Pattern Generation (TPG)
– Response verification
• Random pattern
generation,
very long tests
• Response compression
BIST
Control Unit
IC
Circuitry Under Test
CUT
Test Response Analysis (TRA)
Technical University Tallinn, ESTONIA
Introduction: SoC BIST
Optimization:
-
Embedded Tester
Core 1
Test
Controller
BIST
Test access
mechanism
testing time 
Core 2 cost 
memory
power consumption 
hardwareBIST
cost 
test quality 
Tester
Memory
BIST
Core 3
BIST
Core 4
BIST
Core 5
System on Chip
Technical University Tallinn, ESTONIA
Course Work. Investigations of BIST
• Design of a circuit
• Evaluation of the testability of the circuit
• Redesign for testability
– Control points selection, optimization
– Scan path, optimization
• Built-in self-test. Design of solutions
• Experimental research
Technical University Tallinn, ESTONIA
Course Work. Introduction
• In-circuit
– Test pattern generation
Test Pattern Generation (TPG)
– Response verification
• Pseudorandom test
generation,
very long tests
• Hybrid test solutions
• Response compression
BIST
Control Unit
IC
Circuitry Under Test
CUT
Test Response Analysis (TRA)
Technical University Tallinn, ESTONIA
Course Work. Description of the Circuit
Test Generator - LFSR
4
A B C
x
z
1. Design of a combinational circuit
for the following functionality
k1, k2
If x = 0, z = 0, then Y = k1A + k2B, else
k3, k1
if x = 0, z = 1, then Y = k3A - k1C, else
k1 , k2 ,
k3
MUX
if x = 1, z = 0, then
Y = (k1A  k1B  k2C)  (k3C  NOT (k3A)  k1B),
k4 , k5 ,
k6
else
4
Y
if x = 1, z = 1, then Y = k4A2 + k5A + k6
Interface
Signature Analyzer
Coefficients ki can be found on the
next slide
Technical University Tallinn, ESTONIA
Coefficients for the Course Work Versions
Vers.
No.
k1
k2
k3
k4
k5
k6
Vers
no.
k1
k2
k3
k4
k5
k6
1
1
1
1
0,1
0,2
0,5
8
1
1
1
1,5
0,1
0,5
2
1
1
0
0,1
0,2
1,0
9
1
1
0
1,5
0,1
1,0
3
1
0
1
0,1
0,2
2,0
10
1
0
1
1,5
0,4
2,0
4
1
0
0
0,1
0,2
3,0
11
1
0
0
1,5
0,4
3,0
5
0
1
1
0,1
1,0
0,5
12
0
1
1
1,5
0,8
0,5
6
0
1
0
0,1
1,0
1,0
13
0
1
0
1,5
0,8
1,0
7
0
0
1
0,1
2,0
2,0
14
0
0
1
1,5
1,5
2,0
Technical University Tallinn, ESTONIA
Course Work. Design of Interface Versions
Test Generator - LFSR
4
A B C
x
z
2. Use three different interface versions for
experiments: 1 bit, 2-bit and 4- or more bit
interfaces for respective n-bit Signature
Analyzers
k1, k2
The types of interface:
k3, k1
k1 , k2 ,
k3
Y
MUX
2
2
4
Y
Y
k4 , k5 ,
1)
k6

2)


3)
n bit SA
4
Y
Interface
1 bit SA
2 bit SA
Signature Analyzer
Technical University Tallinn, ESTONIA
Course Work. Design of a Testable Circuit
3.
Enter the designed gate-level (AND, OR, NOT) combinational
circuit into the computer, using CADENCE circuit editor
4.
Generate test patterns with Turbo-Tester (TT) ATPG. If the fault
coverage is 100%, remove one or more patterns from the test
set, so that at least two faults remain undetected.
5.
Improve the testability of the circuit to reach again 100% fault
coverage with the updated test set
OP
Block 1
1
Block 2
1- controllability:
CP = 0 - normal working mode
CP = 1 - controlling Block 2
with signal 1
CP
Technical University Tallinn, ESTONIA
Course Work. Observability Investigation
6. Analyze two different testability improvement solutions:
-
Separate pins for all observability points
-
Single joint pin for all observability points
Draw the graphics for both cases for the function P = f(T) where P is
fault coverage, and T is test length

Technical University Tallinn, ESTONIA
Course Work. Design of a Test Generator
BILBO - Built- In Logic
Block Observer:
7.
Generate test patterns by the BILBO
tool for 10 different polynomials, and
find the best structure for the LFSR
LFSR - Test Pattern Generator
Report for all 10 experiments the
maximum achievable fault coverage,
and fix the minimum test length
needed for that
Combinational circuit
Calculate the increase of the circuit
size (in number of 2-input gates) due
to adding of the self-test circuitry
LFSR - Signature analyzer
Technical University Tallinn, ESTONIA
Course Work. Design of a Test Generator
CSTP - Circular Self-Test
Path:
LFSR - Test Pattern Generator
8.
Repeat the previous task for the
case of using CSTP ("Circular
Self Test Path") for self-test
purposes
& Signature analyser
Combinational circuit
Technical University Tallinn, ESTONIA
Course Work. Design of a Signature Analyzer
Test Generator - LFSR
4
9. Carry out experiments with the best
test set found in task 7 for 4 different
Signature Analyzers: 1-bit, 2-bit, 4bit, and 8-bit
4
A B C
x
Y
z

1)
k1, k2
1 bit SA
k3, k1
k1 , k2 ,
k3
Y
MUX
2
2)
k4 , k5 ,
2


k6
2 bit SA
4
Y
4
Y
Interface
3)
n bit SA
Calculate the fault coverages
Draw the graphic P = f(SA), where P is
the fault coverage and
SA – is the number of bits in the
Signature Analyzer
Draw 4 graphics P = f(T), for 4 SA
cases, where
T – is the test length 5, 10, 15, 20
etc. up to P = 100%
Explain the graphics
Signature Analyzer
Technical University Tallinn, ESTONIA
Course Work. Store-and-Generate BIST
The main motivations of
using random patterns
are:
- low generation cost
- high initial efeciency
Problem: low fault coverage
Long PR test:
Pseudorandom
test:
2n-1
0
Fault Coverage
Hard
to test
faults
Using many seeds:
Pseudorandom
test:
2n-1
0
Time
Technical University Tallinn, ESTONIA
Course Work. Store-and-Generate BIST
10. Synthesize an optimal BIST, using "store & generate“ architecture.
Chose for that the best BILBO structure and ja the 100% test with length
N. Minimize the number of seeds to be stored in the memory
ROM
ADR
Counter 2
TPG
UUT
RD
Counter 1
CL
11. Compare the results in tasks 4, 5, 7, 8 and 10. Which solution is the best
and why? Draw the block-level final structure of the selected best BIST
solution.
12. Present a report of the course work.
Technical University Tallinn, ESTONIA