Transcript 硬體描述語言 Verilog HDL

Graduate Institute of Electronics Engineering, NTU
數位系統設計
901-43500
臺大電機系/電子所
吳安宇教授
代課：趙之昊<[email protected]>
Slide modified from Prof. Wu’s DSD Lecture Note in 2010 Spring
2011/2/23
ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
課程網頁
http://access.ee.ntu.edu.tw/
=> course => Digital System Design
ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
Objective
Digital system design plays an important role
in implementing digital functions in modern
system-on-chip (SOC) design.
In this course, we will focus on developing the
design skills for undergraduate students so
that they can be familiar with state-of-the-art
digital front-end design skills and flow.
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 3
Graduate Institute of Electronics Engineering, NTU
Course Content (I)
 Firstly, we will introduce the Hardware Description Language
(HDL) and general front-end cell-based design flow. The
chosen HDL is Verilog. We will formally cover:
 HDL language syntax (basics)
 Semantics and coding guideline (how to write elegant codes)
 Coding for synthesis (how to write synthesizable codes;
hardware design concept)
 Reuse manual methodology (RMM) – How to create “reusable”
codes for IP (Intellectual property) reuse
 Front-end cell-based synthesis flow (how to use to state-of-theart synthesis tools)
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 4
Graduate Institute of Electronics Engineering, NTU
Course Content (II)
 Secondly, we will ask students to design and implement an
advanced MIPS CPU. It is based on the knowledge of
“Computer Architecture.” The assignment covers:
 RT-level design of major blocks such as arithmetic logic unit (ALU),
control unit, register file, cache unit, etc.
 HDL coding, simulation, synthesis
 Integration of whole design and enabling the execution of MIPS
R32 binary codes
 Instruction set architecture (ISA) development and extension
 Enhanced RISC-based CPU design with Pipelining, Forwarding,
and Hazard Control
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 5
Graduate Institute of Electronics Engineering, NTU
Homework
Five homework
1.
2.
3.
4.
Practice of Structural Verilog Coding
Practice of Behavior-Level Verilog Coding
Design of a Single Cycle MIPS Processor
Design of a Cache Unit
Individual
Homework
5. Topic Selected from Cell-Based IC Design
Contest
Team
Homework
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 6
Graduate Institute of Electronics Engineering, NTU
Final Project
Design of a Pipelined MIPS Processor with
Cache Unit:
Baseline
 Implement specified instruction set (30~40 instructions)
 Combine the components built in hw1~hw4
 Solve data/control/branch hazards
 Execute given binary codes and output correct results
Extension
 Implement MUL/DIV/MAC instructions
 Pipeline ALU and handle hazards from ALU pipelining
 Other selected topics
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 7
Graduate Institute of Electronics Engineering, NTU
Course Schedule (1)
週數 日期
課程規劃
講師
課程內容
W1 2/23 Introduction
趙之昊
Course Overview,
Digital System Design Introduction
W2 3/2
HDL1
陳郁豪
Fundamentals of
Hardware Description Language (Ch1 - 3)
W3 3/9
HDL2
陳郁豪
Logic Design at Register Transfer Level (Ch 4,
7)
W4 3/16
HDL3
蘇冠羽
Logic Design with Behavior Coding,
Design Verification Tool (Ch 8 - 10)
W5 3/23
HDL4
蘇冠羽
Testbench Writing,
Synthesizable Coding of Verilog
W6 3/30
HDL5
馮紹惟
Complexity Management,
Improving Timing/Area/Power
W7 4/6
Break
張恩瑞
Synthesis Overview and Tool Usage
W8 4/13 Synthesis1
W9 4/20
作業宣佈
作業繳交
HW1
HW2
HW1
HW3
HW2
Midterm
Exam
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 8
Graduate Institute of Electronics Engineering, NTU
Course Schedule (2)
週數 日期
課程規劃
講師
課程內容
作業宣佈
作業繳交
W10 4/27
Synthesis2
張恩瑞
Advanced Topics on Synthesis
HW4
HW3
W11 5/4
Design Guideline
鍾明翰
Design Guideline: From Spec to Circuit
W12 5/11
Design Issues for
MIPS Processor(1)
陳坤志
MIPS Overview, Memory Hierarchy
Project &
HW5
HW4
W13 5/18
Design Issues for
MIPS Processor (2)
陳坤志
Pipelined Architecture of MIPS
W14 5/25
Speech Invitation
Speaker
(To-be-defined)
W15 6/1
Break
W16 6/8
Project Check
Point
吳安宇
教授
Oral presentation
W17 6/15
Break
W18 6/22
Project
Presentation
吳安宇
教授
Oral presentation
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
HW5
Project
pp. 9
Graduate Institute of Electronics Engineering, NTU
Textbooks
 (Main Verilog coding textbook)
“Verilog HDL: Digital design and modeling,”
Joseph Cavanagh, CRC Press, 2007.
 (Reference CPU textbook)
“Computer organization and design: The
hardware/software interface,”
David A. Patterson and John L. Hennessy,
2008, 4th Edition.
 (Reference Verilog coding textbook )
“Digital system designs and practices:
Using Verilog HDL and FPGAs,"
Ming-Bo Lin, Wiley, 2008.
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 10
Graduate Institute of Electronics Engineering, NTU
Course Grading




Homework: 30%
Midterm Exam: 30%
Final Project: 35%
Impression: 5%
(Attendance & Attitude).
 Previous results:
12
10
8
6
4
2
0
70-74 75-79 80-84 85-89 90-94 95-99
972
Original
972
Final
982
Original
982
Final
Mean
81.15
88.31
85.30
88.26
Stdv.
13.96
9.75
8.39
7.30
12
10
8
6
4
2
0
70-74 75-79 80-84 85-89 90-94 95-99
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 11
Graduate Institute of Electronics Engineering, NTU
Suggested Background


Programming Language : Required
Logic Design : Required

Computer Organization and Design: Suggested

VLSI Design and VLSI/EDA tools: Optional
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 12
Graduate Institute of Electronics Engineering, NTU
Limitation
Limit
39 students, 13 teams
3 students as a team for hw5 and project
Priority:
1.
2.
3.
4.
5.
6.
EE3
EE4
EE2
EE1
Other departments
Graduate students.
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 13
Graduate Institute of Electronics Engineering, NTU
Major Related Courses
 Computer Architecture
 http://access.ee.ntu.edu.tw/course/CA_992/
 Cover domain knowledge of computer organization and the
relationship between hardware and software
 Textbook: David A. Patterson, and John L. Hennessy, “Computer
Organization and Design – The Hardware/Software Interface”,
4th Edition, Morgan Kaufman Publishers, Inc., 2009.
 Digital Circuit Design Lab
 Project oriented practice of design and implementation of real
systems
 FPGA-based design flow
 Computer-aided VLSI System Design (CVSD) –
graduate course of NTUGIEE
 Cover more topics and back-end flow of cell-based IC design
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 14
Graduate Institute of Electronics Engineering, NTU
High-performance Digital
Design in SoC Era
ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
IC Design and Implementation
Idea
Design
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 16
Graduate Institute of Electronics Engineering, NTU
Digital IC Design Flow
1.
2.
3.
4.
Concept/Application
Function/Spec. definition
Algorithm exploration
Architecture design
1. Divide-and-conquer
2. Sub-module design
3. Design verification
5. System prototyping (need
training!!)
1. RTL design
2. Verilog
Coding/Schematic
Design
3. Cell-based IC design
flow / FPGA design flow
W1: DSD Course Overview 2011.2.23
operand_a
operand_b
4
4-bit 2's
Complement
Add/Sub
4
4
result
mode
a3
carry
out
An-Yeu Wu
b3
a2
b2
a1
b1
a0
b0
FA3
FA2
FA1
FA0
result3
result2
result1
result0
mode
pp. 17
Graduate Institute of Electronics Engineering, NTU
System Specification
Partition
IO Spec.
IO Timing Spec.
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 18
Graduate Institute of Electronics Engineering, NTU
Algorithm Mapping and Architecture Design
System/Algorithm Level
RTL Level
Description
of hardware
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 19
Graduate Institute of Electronics Engineering, NTU
Cell-Based IC Design Flow
Design Capture
Functional
Design Iteration
HDL
Pre-Layout
Simulation
Structural
Logic Synthesis
Front
-End
Floorplanning
Post-Layout
Simulation
Placement
Circuit Extraction
Routing
Physical
Back
-End
Tape-out
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 20
Graduate Institute of Electronics Engineering, NTU
Brief Overview of Digital System
Design
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 21
Graduate Institute of Electronics Engineering, NTU
The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
Cost:17,470 Pounds
in Year 1832
Mechanical, using gears, decimal notation
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 22
Graduate Institute of Electronics Engineering, NTU
ENIAC -The first electronic computer (1946)
Use Vacuum Tubes as Switching Components (Binary)
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 23
Graduate Institute of Electronics Engineering, NTU
Now: Computer Everywhere
Advances of VLSI Technology Brings Computer Everywhere
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 24
Graduate Institute of Electronics Engineering, NTU
Technologies for building processors and
memories
 Vacuum tube
An electronic component, predecessor of the
transistor, that consists of a hollow glass tube about
5 to 10 cm long from which as much air has been
removed as possible and which uses an electron
beam to transfer data
 Transistor
An ON/OFF switch controlled by an electric signal
 Very large scale integrated (VLSI) circuit
A device containing hundreds of thousands to
millions of transistors
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 25
Graduate Institute of Electronics Engineering, NTU
Vacuum Tube
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 26
Graduate Institute of Electronics Engineering, NTU
The Transistor Revolution
First transistor
Bell Labs, 1948
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 27
Graduate Institute of Electronics Engineering, NTU
Discrete Transistors
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 28
Graduate Institute of Electronics Engineering, NTU
The MOS Transistor
Polysilicon
Aluminum/Cu
Channel length: The distance between Source and Drain
0.18um/0.13um: this year
90nm: next year
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 29
Graduate Institute of Electronics Engineering, NTU
The First Integrated Circuits
Bipolar logic
1960’s
ECL 3-input Gate
Motorola 1966
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 30
Graduate Institute of Electronics Engineering, NTU
Gate and Circuit Level Design
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 31
Graduate Institute of Electronics Engineering, NTU
Mapping of Layout to IC Layers
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 32
Graduate Institute of Electronics Engineering, NTU
Layout of an CMOS Inverter
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 33
Graduate Institute of Electronics Engineering, NTU
Physical Design
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 34
Graduate Institute of Electronics Engineering, NTU
Physical Layout of your design
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 35
Graduate Institute of Electronics Engineering, NTU
The “Timing Closure” Problem
Iterative Removal of Timing Violations (white lines)
Courtesy Synopsys
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 36
Graduate Institute of Electronics Engineering, NTU
The chip manufacturing process
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 37
Graduate Institute of Electronics Engineering, NTU
Humorous
Analogy between
Chip Fabricating
Process and
Pizza Making
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 38
Graduate Institute of Electronics Engineering, NTU
Moore’s Law
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION
 In 1965, Gordon Moore noted that the number of transistors on
a chip doubled every 18 to 24 months.
 He made a prediction that semiconductor technology will
double its effectiveness every 18~24 months
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
Electronics, April 19, 1965.
pp. 39
Graduate Institute of Electronics Engineering, NTU
Moore’s Law: Driving Technology Advances
 Logic capacity doubles per IC at regular intervals (1965).
 Logic capacity doubles per IC every 18 months (1975).
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 40
Graduate Institute of Electronics Engineering, NTU
Technologies for building processors and
memories
Relative performance per unit cost of technologies used in computers
over time
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 41
Graduate Institute of Electronics Engineering, NTU
Engineering Productivity Gap
 Engineering
productivity has not
been keeping up with
silicon gate capacity for
several years.
 Companies have been
using larger design
teams, making
engineers work longer
hours, etc., but clearly
the limit is being
reached.
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 42
Graduate Institute of Electronics Engineering, NTU
Why must HDL tools & IP Reuse?
Design productivity crisis:
Divergence of potential design complexity
and designer productivity
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 43
Graduate Institute of Electronics Engineering, NTU
Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
D
n+
pp. 44
Graduate Institute of Electronics Engineering, NTU
HDL and Moore’s Law
HDL – Hardware Description Language
Why use an HDL ?
Hardware is becoming very difficult (and too big!)
to design directly
HDL is easier and cheaper to explore different
design options
Reduce time and cost to verify your digital designs
in VLSI implementations
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 45
Graduate Institute of Electronics Engineering, NTU
Verilog HDL
Feature
HDL has high-level programming language
constructs and constructs to describe the
connectivity of your circuit.
Ability to mix different levels of abstraction freely
One language for all aspects of design, test, and
verification
Functionality as well as timing
Concurrently simulate behaviors of multiple
hardware blocks in simulator
Support timing simulation for your design
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 46
Graduate Institute of Electronics Engineering, NTU
Level of Abstraction for Design and
Verification
System
concept
Algorithm
Increasing
behavioral
abstraction
Architecture
Increasing
detailed
realization &
complexity
Register Transfer Level
Gate Level
Transistor Level
W1: DSD Course Overview 2011.2.23
2009.2.18
An-Yeu Wu
pp. 47
Graduate Institute of Electronics Engineering, NTU
Verilog HDL in Different Level
Behavioral
level of
abstraction
System
Algorithm
RTL
Design Model Domain
Abstract
Structural
Physical
Architecture
Synthesis
Architecture
Design
RTL level
Synthesis
Structural
Design
Verification
Gate
Logic
Design
Verification
Switch
W1: DSD Course Overview 2011.2.23
Logic level
Synthesis
Layout
Design
Verification
An-Yeu Wu
pp. 48
Graduate Institute of Electronics Engineering, NTU
Cell-based IC Design Flow
Back-End
Design Specification
Pre-Synthesis
Sign-Off
Cell Placement, Scan
Chain & Clock Tree
Insertion, Cell Routing
Design Partition
Synthesize and Map
Gate-Level Netlist
Verify Physical &
Electrical Design Rules
Design Entry-Verilog
Behavioral Modeling
Post-Synthesis
Design Validation
Extract Parasitics
Simulation/Functional
Verification
Post-Synthesis
Timing Verification
Post-Layout
Timing Verification
Design Integration &
Verification
Test Generation &
Fault Simulation
Design Sign-Off
Production-Ready
Masks
Front-End Designs
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 49