Transcript 硬體描述語言Verilog HDL

Graduate Institute of Electronics Engineering, NTU
Course Schedule (1)
週數 日期
課程規劃
講師
課程內容
Fundamentals of
Hardware Description Language (Ch1 - 3)
W2 3/2
HDL1
陳郁豪
W3 3/9
HDL2
陳郁豪 Logic Design at Register Transfer Level (Ch 4, 7)
W4 3/16
HDL3
蘇冠羽
Logic Design with Behavior Coding,
Design Verification Tool (Ch 8 - 10)
W5 3/23
HDL4
蘇冠羽
Testbench Writing,
Synthesizable Coding of Verilog
W6 3/30
HDL5
馮邵惟
Complexity Management,
Improving Timing/Area/Power
W7 4/6
Break
W9 4/20
作業繳交
Course Overview,
Digital System Design Introduction
W1 2/23 Introduction 趙之昊
W8 4/13 Synthesis1 張恩瑞
作業宣佈
HW1
announce
HW2
announce
HW1
deadline
HW3
announce
HW2
deadline
Synthesis Overview and Tool Usage
Midterm
Exam
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 1
Graduate Institute of Electronics Engineering, NTU
Course Schedule (2)
週數
日期
課程規劃
講師
課程內容
作業宣佈
作業繳交
W10
4/27
Synthesis2
張恩瑞
Advanced Topics on Synthesis
HW4
announce
HW3
deadline
W11
5/4
Design Guideline
鍾明翰
Design Guideline: From Spec to Circuit
& FPGA Lab
W12
5/11
Design Issues for
MIPS Processor(1)
陳坤志
MIPS Overview, Memory Hierarchy
Project
W13
Design Issues for
5/18
MIPS Processor (2)
陳坤志
Pipelined Architecture of MIPS
HW5
Announce
(5/21早上)
W14
5/25
Speech Invitation
Bor-Sung
Liang
CPU Design
W15
6/1
Break
W16
6/8
Project Check
Point
陳郁豪
Project Check Point
W17
6/15
Break
W18
6/22 or
6/28
Project
Presentation
吳安宇
教授
Oral presentation
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
HW4
deadline
HW5
deadline
Project
deadline
pp. 2
Graduate Institute of Electronics Engineering, NTU
HW5:IC Design Contest
Announce at 5/21 9:00AM(星期六)
Deadline at 5/24 11:59AM(星期二)
Score: Area*time
Project Presentation
6/22(星期三) or 6/28(星期二) 1:00PM
W1: DSD Course Overview 2011.2.23
An-Yeu Wu
pp. 3