Low Power and High Speed Multi Threshold Voltage Interface Circuits By

Sherif A. Tawfik and Volkan Kursun

Presented by Ramasamy Ethiraj

Contents

• Introduction • Standard Feedback-Based Level Converters • Proposed Multi-Vth Level Converters • Delay and Power consumption of level Converters - Comparison of level converters - The performance of level converters under Supply Voltage and Process Parameter Variations - Multi Vth-CMOS Technology • CONCLUSION

Introduction

• Scaling the supply voltage to reduce the power • Lower supply will degrade the speed • Multi-V DD Techniques and Conventional Level converters are introduced.

• Conventional Level converters will introduce DC current and feedback circuit (hence slow response) • Multi-Vth Level converters will eliminate DC current and Feedback circuit.

Standard Level Converters 1 (LC1)

• V DDL is directly connected to M3 & M4 – DC path. So high power • Feedback circuit – more delay.

• M1 & M2 should be large, because V DDL Result in large capacitance and area is directly connected.

Standard Level Converters 2 (LC2)

• V DDL is not directly connected to PMOS – still some DC current • Feedback circuit – more delay.

• More device count- more delay and power • M2 should be large, because V DDL large capacitance and area is directly connected. Result in

Proposed Multi-Vth Level Converter1 (PC1)

• V th-M2 should be more negative than V DDL –V DDH to avoid DC current • No feedback circuit – less delay.

• less device count- less delay, area and power • Smaller transistor sizes.

Proposed Multi-Vth Level Converter2 (PC2)

• V th-M2 should be more negative than V DDL –V DDH to avoid DC current • Multi V th is used for M3. • Lowest delay compare to other converters • No feedback circuit – less delay.

• Smaller transistor sizes.

Proposed Multi-Vth Level Converter2 (PC2)

• V th-M2 should be more negative than V DDL –V DDH to avoid DC current • M3,M4,C is removed for lower V DDL • No feedback circuit – less delay.

• Smaller transistor sizes.

Simulation Setup

• 0.18um technology • V DDH = 1.8V

• Simulated for different V DDL : 0.5, 1 and 1.2V

• Wn = Wmin, Wp = 2.5Wn

• Delay is measured between input of I D and Node2 • Power consumption measured for entire setup

Optimum Delay and Power measurements

Normalized to LC2

The performance of level converters under Supply Voltage and Process Parameter Variations

Power and Delay comparison – LC2 vs. PC2 for Power optimized circuit (VDDL = 1.2V)

Power and Delay comparison – LC2 vs. PC1 for Power optimized circuit (V DDL = 1V)

Power and Delay comparison – LC2 vs. PC1 for Power optimized circuit (VDDL = 0.5V)

V th-M2 vs. Power and Delay

Conclusions

•

Multi-V th level converters has up to 78% less delay compare to standard level converters • 70% less power consumption • Less Device count and size – minimum Area • Wide range of threshold voltages • High speed and low power.

Thank You