Platform Conference July 2002 Template
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Transcript Platform Conference July 2002 Template
Memory Design
Considerations That Affect
Price and Performance
Bill Gervasi
Technology Analyst, Transmeta
Chairman, JEDEC Memory Parametrics
[email protected]
Posed at the Last Conference
Why will DDR-I at 400 MHz data rate be a
“boutique” solution?
Why will DDR-II at 400 MHz data rate be
a “mainstream” solution?
Agenda
JEDEC/Industry Roadmap
Factors for Market Acceptance
Difficulties in Achieving 400 MHz
Factors Affecting Cost
Wild Cards – What Can Change?
5400MB/s
RAM Evolution
4300MB/s
Mainstream
Memories
3200MB/s
“DDR II”
2700MB/s
2100MB/s
“DDR I”
Simple,
incremental
steps
Factors for Market Acceptance
Industry Focus
Number of Competing Suppliers
JEDEC standard
Laws of Physics
Industry Focus
The JEDEC roadmap represents the industry
focus for mainstream products
DDR-I tops out at 333 MHz data rate
DDR-II starts at 400 MHz data rate
This DOES NOT mean that DDR-I at 400
MHz data rate will not ship in volume
It DOES mean that there will be price
premiums for this speed bin
What do I mean by “Focus”?
There is serious work to hit 400 MHz
Vendor interoperable solutions
Mix and match module configurations
Signal integrity analysis
We are counting picoseconds
No JEDEC standard yet proposed for DDR-I
at 400 MHz data rate
For Example…
How we are getting more refined in timing
analysis with DDR-II…
The Charge Transfer Model for input
timing measurement and derating
DDR-I Input Timing Model
CLOCK
CLOCK
Setup
Hold
INPUT
Timing derating by input signal slew rate:
1.0V/ns = base value
0.5V/ns = base value + 50ps
0.4V/ns = base value + 100ps
This got us through DDR333…
However…
This simplified model was good enough
for DDR333 data rates, but leaves
picoseconds of available timing lying
around needed for 400+!!!
DDR266 Data Setup/Hold = 750 ps
DDR333 Data Setup/Hold = 600 ps
DDR400 Data Setup/Hold = 400 ps
DDR533 Data Setup/Hold = 350 ps
Can’t waste
time!!!
“Focus” on Input Timing
INPUT
tEXT
tINT
tT
DDR-II Charge Transfer Timing Model
All inputs have a slew rate dependent aspect tEXT
and an independent aspect tINT
Summing tEXT + tINT gives input transition time tT
Transition time tT has min and max values
Differential input transitions inherently different
tEXT for Slow Slew Rate, Single Ended
VIHAC =
VSAT
AT = Charge
to Transition
VIHDC
VREF
tEXT
VILDC
VILAC=
VSAT
t EXT
2 * AT
slew
tINT
tEXT for Fast Slew Rate, Single Ended
VSAT = Saturation
Voltage
VIHAC =
VSAT
AT = ASAT + AADD
ASAT = Charge
to Saturation
VIHDC
VREF
AADD = Charge
after Saturation
tSAT
VILDC
tEXT
VILAC =
VSAT
tINT
t EXT t SAT
( AT ASAT )
VSAT
tEXT for Slow Slew Rate, Differential
VIHAC =
VSAT
AT = Charge
to Transition
VIHDC
VREF
VILDC
VILAC =
VSAT
tEXT
tINT
tEXT for Fast Slew Rate, Differential
AT = ASAT + AADD
VIHAC =
VSAT
VIHDC
VREF
VILDC
VILAC =
VSAT
tEXT
tINT
“Focus” on Timing
CLOCK
tTmin
CLOCK
Setup
INPUT
tTmax
DDR-II Charge Transfer Timing Model
Setup = tTmax of input - tTmin of reference
“Focus” on Timing
CLOCK
tTmax
CLOCK
Hold
INPUT
tTmin
DDR-II Charge Transfer Timing Model
Hold = tTmax of reference - tTmin of input
How does this help…?
The Charge Transfer Model gives a higher
accuracy for setup and hold relationships
It also provides a way to accurately describe
derating for input slew rate
These models are negotiated with all suppliers
to define an industry standard
DDR-II Input Derating Tables
Strobe (mV/ps avg)
0.5
1.0
2.0
0.5
+
+
1.0
0
+
+
2.0
SETUP
Addr (mV/ps)
Data (mV/ps)
SETUP
0.5
1.0
2.0
0.5
+
+
1.0
0
+
+
2.0
Strobe (mV/ps avg)
HOLD
0.5
1.0
2.0
+
+
1.0
+
+
0
2.0
0.5
Addr (mV/ps)
Data (mV/ps)
HOLD
Clock (mV/ps avg)
Clock (mV/ps avg)
0.5
1.0
2.0
+
+
1.0
+
+
0
2.0
0.5
Derating Using Charge Transfer
Accuracy from derating both signals and references
Result is a two dimensional matrix relating inputs & their
references
Identified inherent asymmetries in derating of setup & hold
when mixing single ended with differential signals
Memory module mixes impact slew rates
The Charge Transfer model controls system cost by
enabling more complex timing analysis
Charge Transfer on DDR-I?
This model would also help design high
speed DDR-I systems
However, the work to retrofit this to DDR-I
needs to be done to benefit from it
DDR-II Improvements
DDR-II introduces technical improvements that
reduce the cost of achieving high speeds
Prefetch 4
Differential data strobe
I/O Calibration
Lower I/O Voltage
On-Die Termination
Prefetch 4
Moving to the Next Level
Today’s SDRAM architectures assume an
inexpensive DRAM core timing
DDR I (DDR200, DDR266, and DDR333)
prefetches 2 data bits: increase performance
without increasing timing costs
DDR II (DDR400, DDR533, DDR667) prefetches 4
bits internally, but keeps DDR double pumped I/O
Prefetch 2 Versus 4
CK
READ
data
Core access
time
Prefetch 2
Prefetch 4
Costs $$$
Column cycle
time
Costs $$$
Essentially free
Prefetch Impact on Cost
By doubling the prefetch depth, cycle time for column
reads & writes relaxed, improving DRAM yields
DDR
Family
DDR-I
DDR-II
Prefetch
Data
Rate
Cycle
Time
2
266
7.5 ns
2
333
6 ns
2
400
5 ns
4
400
10 ns
4
533
7.5 ns
4
667
6 ns
Starts to get REAL
EXPENSIVE!
Comparable to
DDR266 in cost
Why Not Prefetch = 8?
DIMM width = 64 bits
PCs use 64b, servers use 128b (2 DIMMs)
64 byte prefetch okay for PC, but…
128 byte prefetch for servers wastes bandwidth
DDR-II must service all applications well to
insure maximum volume minimum cost
Differential Data Strobe
Differential Data Strobe
Just as DDR added differential clock to SDR
DDR II adds differential data strobe to DDR I
Transition at the crosspoint of DQS and DQS
Differential Data Strobe
VREF
DQS
DQS
high time
Normal
balanced
signal
DQS
low time
VREF
DQS
Mismatched
Rise & Fall
signal
Error!
DQS
high
time
DQS
low time
Differential Data Strobe
DQS
DQS
Normal
balanced
signal
VREF
DQS
high time
DQS
low time
DQS
VREF
DQS
Mismatched
Rise & Fall
signal
DQS
high time
DQS
low time
Significantly reduced symmetry error
I/O Calibration
I/O Calibration
Balance pull-up and pull-down driver strength
Reduces timing errors from signal asymmetry
Insures signal rise and fall times are similar
Data
DRAM
Controller
Data
Reference
1.8V I/O Voltage
1.8V Signaling
2.5V
VDDQ
VIHac
VIHdc
VREF
VILdc
VILac
VSS
SSTL_2
1.60V
1.43V
VDDQ
1.25V
1.07V
0.90V
VIHac
VIHdc
VILdc
VILac
VSS
SSTL_18
1.8V
VREF
1.15V
1.03V
0.90V
0.77V
0.65V
0V
I/O Voltage Impact on Timing
Assume 1mV/ps edge slew rate
DDR-I = 700 mV (VILVIH) = 700 ps
DDR-II = 500 mV (VILVIH) = 500 ps
Helps meet the need for speed
Signal integrity is a serious challenge at
DDR-I and 400 MHz data rate
On-Die Termination
On-Die Termination
VTT =
VDDQ 2
Data
Controller
DRAM
DDR-I
DRAM
DDR-II
Data
Controller
VDDQ 2
VDDQ 2
Reduces system cost while improving signal integrity
What Can Change?
Wild Cards
100% yield of 5 ns cycle time cores (magic?)
Industry gets excited about engineering
DDR-I at 400 MHz
DDR-II slow transition from schedule or price
Feature creep
Die penalties
DRAM guys trying to make money for once
Conclusions
DDR-I at 400 will ship in volume but
…not likely to cross over $/bit
Industry focus is on transition to DDR-II
for 400+ MHz data rates
Thank You