Timing is Everything - Discobolus Designs, Home Page
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Transcript Timing is Everything - Discobolus Designs, Home Page
When Timing-Is-Everything …
Charge Transfer Model for
Input Signaling & Referencing
Bill Gervasi
Technology Analyst
[email protected]
([email protected])
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Agenda
•
•
•
•
•
•
Review traditional setup & hold time
Examine impact of signal slew rate
Compare single ended to differential
What about non-monotonic signals?
Looking to the future
Call to action
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Why a New Model?
• Variable Frequency systems expanding
– Fixed frequency systems just needed a
yes/no answer on signal integrity
– Variable frequency systems need more:
calculated based on available data eye
Available operating frequency =
1 (required data eye + crap)
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Traditional Input Timing Model
CLOCK
CLOCK
Setup
Hold
INPUT
Timing derating by input signal slew rate:
1.0V/ns = base value
0.5V/ns = base value + 50ps
0.4V/ns = base value + 100ps
This got us through 266-333 MHz data rates…
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Problems with Traditional Model
• Does not account for differences between
single ended and differential
• Assumes setup & hold remain balanced
• No analytical way to project derating
• No guidance to package developers
• No mechanism to handle non-monotonic
signal transitions
• Leaves important picoseconds wasted
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Charge Transfer Model (CTM)
INPUT
tEXT
tINT
tT
Charge Transfer Timing Model
– All inputs have a slew rate dependent aspect tEXT
and an independent aspect tINT
– Summing tEXT + tINT gives input transition time tT
– Transition time tT has min and max values
– Differential input transitions inherently different
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Factors Affecting Transition
• External factors that are edge rate
dependent
– Package parasitics
– Input stage 1 characteristics including
input type & saturation
• Internal factors that are edge rate
independent
– Internal loading mismatch
– On-chip routing
– Process, voltage, temperature
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Standards Versus Proprietary
• CTM was developed inside JEDEC for DDR2
• Standards require an envelope within which multiple
suppliers specs operate, therefore:
–
–
–
–
I use VREF as an accumulation start threshold
I use VILAC and VIHAC as saturation thresholds
These do not represent all input types, but
They do define a standard way to define the envelope
• Proprietary systems analyses could use real
thresholds for increased application specific accuracy
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
tEXT for Slow Slew Rate, Single Ended, simple model
VIHAC =
VREF + VSAT
AT = Charge
to Transition
VIHDC
VREF
tEXT
tINT
VILDC
tT
VILAC =
VREF - VSAT
Mark Sherwood and Associates
t EXT
All rights reserved
2 * AT
slew
Copyright JANUARY, 2003
When Timing-Is-Everything …
tEXT for Fast Slew Rate, Single Ended, simple model
AT = ASAT + AADD
VSAT = Saturation
Voltage Offset
AADD = Charge
after Saturation
VIHAC =
VREF + VSAT
VIHDC
ASAT = Charge
to Saturation
VREF
tSAT
VILDC
tEXT
tINT
tT
VILAC =
VREF - VSAT
Mark Sherwood and Associates
t EXT t SAT
( AT ASAT )
VSAT
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Internal factors
Copyright JANUARY, 2003
When Timing-Is-Everything …
tEXT for Slow Slew Rate, Differential, simple model
VIHAC =
VREF + VSAT
AT = Charge
to Transition
VIHDC
VREF
VILDC
VILAC =
VREF - VSAT
tINT
tEXT
tT
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
tEXT for Fast Slew Rate, Differential, simple model
AT = ASAT + AADD
VIHAC =
VREF + VSAT
VIHDC
VREF
VILDC
VILAC =
VREF - VSAT
tEXT
tINT
tT
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Applying CTM to Setup & Hold
• Relate input signals (data, address,
command) to reference (clock, strobe)
• Assert tTmax and tTmin characteristics
• Assume inputs and references may have
different input slew rates
• Outcome is a matrix of deratings
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
CTM Setup Time Definition
CLOCK
tTmin
CLOCK
Setup
INPUT
tTmax
Setup = tTmax of input – tTmin of reference
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
CTM Hold Time Definition
CLOCK
tTmax
CLOCK
Hold
tTmin
INPUT
Hold = tTmax of reference – tTmin of input
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
How does this help…?
The Charge Transfer Model gives a higher accuracy for
setup and hold relationships
It also provides a way to accurately describe derating
for input slew rate
Charge Transfer Model gives a method for analyzing
non-monotonic transitions
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Example: DDR2 Input Derating Tables
Strobe (mV/ps avg)
0.5
1.0
2.0
0.5
+
+
1.0
0
+
+
2.0
SETUP
Addr (mV/ps)
Data (mV/ps)
SETUP
0.5
1.0
2.0
0.5
+
+
1.0
0
+
+
2.0
Strobe (mV/ps avg)
HOLD
0.5
1.0
2.0
+
+
1.0
+
+
0
2.0
0.5
Mark Sherwood and Associates
Addr (mV/ps)
Data (mV/ps)
HOLD
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Clock (mV/ps avg)
Clock (mV/ps avg)
0.5
1.0
2.0
+
+
1.0
+
+
0
2.0
0.5
Copyright JANUARY, 2003
When Timing-Is-Everything …
Derating Using Charge Transfer
• Users continue to use VREF crossing for single ended
and crosspoint of differential pair for measurement
• Derating tables correlate measurement to required
setup & hold times
• “Boot-time” slew rate calculations may be needed,
e.g. modules stuffed and total loading
The Charge Transfer Model reduces system
development cost by enabling more complex timing
analysis
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Non-Monotonic Transitions
• Line reflections in complex system loading or enduser configurable systems cause shelves or ringback,
for example…
Memory Slots
Data bus
1-4 loads per slot
Memory
Controller
Address/Command bus
4-36 loads per slot
Clocks
Fixed loading per slot
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Charge Transfer Model for Non-Monotonic Transitions
Ringback here
should not matter
Accumulated charge
reaches mV-ps needed to
trigger input
VIHAC =
VREF + VSAT
VIHDC
VREF
tINT
tEXT
VILDC
tT
VILAC=
VREF - VSAT
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Ringback below accumulation threshold
A3
A1
A2
VIHAC =
VREF + VSAT
VIHDC
VREF
VILDC
tINT
tEXT
tT
VILAC=
VREF - VSAT
Mark Sherwood and Associates
Charge Accumulation =
A1 – A2 + A3
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Copyright JANUARY, 2003
When Timing-Is-Everything …
Next Generation Models
• Characterize and combine input types
– Where tEXT is the same and only tINT is different
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•
•
•
•
More complex geometrical area calculations
More accuracy in accumulation & saturation points
Non-linearities in charge accumulation
Model for ground bounce
Model for power supply noise
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Summary
• Charge Transfer Model separates input signal
characteristics
– Slew rate dependent
– Slew rate independent
• Single ended and differential derate
differently
• Matrix derating tables needed to handle CTM
• Non-monotonics can be dealt with
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Call to Action
• Extend IBIS models with CTM
• Need logic analysis tools for calculating
charge accumulation
– Accumulation threshold
– Saturation threshold
– Comprehend setup & hold timing derating
• mV-ps accumulation area
• Line up or mark tT(min) & tT(max)
• Single ended versus differential accumulation
• Looking ahead
– Algorithmic accumulation model
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003
When Timing-Is-Everything …
Thank You
Mark Sherwood and Associates
All rights reserved
Copyright JANUARY, 2003